Datasheet

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SBOS266E − JUNE 2003 − REVISED AUGUST 2008
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19
Dividing this expression by the noise gain
(NG = (1 + R
F
/R
G
)) will give the equivalent input-re-
ferred spot noise voltage at the noninverting input, as
shown in Equation 2:
E
N
+ E
NI
2
)
ǒ
I
BN
R
S
Ǔ
2
) 4kTR
S
)
ǒ
I
BI
R
F
NG
Ǔ
2
)
4kTR
F
NG
Ǹ
Evaluating these two equations for the circuit and com-
ponent values shown in Figure 1 will give a total output
spot noise voltage of 19.3nV/√Hz and a total equivalent
input spot noise voltage of 9.65nV/√Hz. This is including
the noise added by the resistors. This total input-re-
ferred spot noise voltage is not much higher than the
9.2nV/√Hz specification for the op amp voltage noise
alone.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage-feed-
back op amp allows good output DC accuracy in a wide
variety of applications. The power-supply current trim
for the OPA832 gives even tighter control than compa-
rable products. Although the high-speed input stage
does require relatively high input bias current (typically
5µA out of each input terminal), the close matching be-
tween them may be used to reduce the output DC error
caused by this current. This is done by matching the DC
source resistances appearing at the two inputs. Evalu-
ating the configuration of Figure 3 (which has matched
DC input resistances), using worst-case +25°C input
offset voltage and current specifications, gives a worst-
case output offset voltage equal to:
(NG = noninverting signal gain at DC)
±(NG × V
OS(MAX)
) ± (R
F
× I
OS(MAX)
)
= ±(2 × 10mV) ± (400Ω × 1.5µA)
= ±10.6mV
A fine-scale output offset null, or DC operating point ad-
justment, is often required. Numerous techniques are
available for introducing DC offset control into an op
amp circuit. Most of these techniques are based on add-
ing a DC current through the feedback resistor. In se-
lecting an offset trim method, one key consideration is
the impact on the desired signal path frequency re-
sponse. If the signal path is intended to be noninverting,
the offset control is best applied as an inverting sum-
ming signal to avoid interaction with the signal source.
If the signal path is intended to be inverting, applying the
offset control to the noninverting input may be consid-
ered. Bring the DC offsetting current into the inverting
input node through resistor values that are much larger
than the signal path resistors. This will insure that the
adjustment circuit has minimal effect on the loop gain
and hence the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature will set the
maximum allowed internal power dissipation, as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 150°C.
Operating junction temperature (T
J
) is given by
T
A
+P
D
×θ
JA
. The total internal power dissipation (P
D
)
is the sum of quiescent power (P
DQ
) and additional
power dissipated in the output stage (P
DL
) to deliver
load power. Quiescent power is simply the specified no-
load supply current times the total supply voltage
across the part. P
DL
will depend on the required output
signal and load; though, for resistive loads connected
to mid-supply (V
S
/2), P
DL
is at a maximum when the
output is fixed at a voltage equal to V
S
/4 or 3V
S
/4. Under
this condition, P
DL
=V
S
2
/(16 × R
L
), where R
L
includes
feedback network loading.
Note that it is the power in the output stage, and not into
the load, that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an OPA832 (SOT23-5 package) in the circuit of
Figure 3 operating at the maximum specified ambient
temperature of +85°C and driving a 150Ω load at mid-
supply.
P
D
= 10V × 3.9mA + 5
2
/(16 × (150Ω || 400Ω)) = 53.3mW
Maximum T
J
= +85°C + (0.053W × 150°C/W) = 93°C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations
may require lower ensured junction temperatures. The
highest possible internal dissipation will occur if the load
requires current to be forced into the output at high out-
put voltages or sourced from the output at low output
voltages. This puts a high current through a large inter-
nal voltage drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency
amplifier like the OPA832 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance in-
clude:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on
the noninverting input, it can react with the source im-
pedance to cause unintentional bandlimiting. To reduce
unwanted capacitance, a window around the signal I/O
pins should be opened in all of the ground and power
planes around those pins. Otherwise, ground and pow-
er planes should be unbroken elsewhere on the board.
b) Minimize the distance ( < 0.25”) from the power-sup-
ply pins to high-frequency 0.1µF decoupling capacitors.
At the device pins, the ground and power-plane layout
(2)