Datasheet

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SBOS266E − JUNE 2003 − REVISED AUGUST 2008
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17
This circuit removes the peaking by bootstrapping out
any parasitic effects on R
G
. The input impedance is still
set by R
M
as the apparent impedance looking into R
G
is very high. R
M
may be increased to show a higher in-
put impedance, but larger values will start to impact DC
output offset voltage. This circuit creates an additional
input offset voltage as the difference in the two input
bias current times the impedance to ground at V
IN
.
Figure 8 shows a comparison of small-signal frequency
response for the unity-gain buffer of Figure 2 (with V
CM
removed from R
G
) compared to the improved approach
shown in Figure 7.
OPA832
V
OUT
V
IN
R
G
400
Ω
R
O
75
Ω
R
F
400
Ω
R
M
50
Ω
+5V
Figure 7. Improved Unity-Gain Buffer
UNITY-GAIN BUFFER
This buffer can simply be realized by not connecting R
G
to ground. This type of realization shows a peaking in
the frequency response. A similar circuit that holds a flat
frequency response giving improved pulse fidelity is
shown in Figure 7.
6
3
0
−
3
−
6
−
9
−
12
Frequency (MHz)
Gain (dB)
1 10 100 400
G=+1Buffer
R
G
Floating
G = +1 Buffer
Figure 5
Figure 8. Buffer Frequency Response
Comparison
OPERATING SUGGESTIONS
GAIN SETTING
Setting the gain for the OPA832 is very easy. For a gain
of +2, ground the −IN pin and drive the +IN pin with the
signal. For a gain of +1, either leave the −IN pin open
and drive the +IN pin or drive both the +IN and −IN pins
as shown in Figure 7. For a gain of −1, ground the +IN
pin and drive the −IN pin with the input signal. An exter-
nal resistor may be used in series with the −IN pin to re-
duce the gain. However, since the internal resistors (R
F
and R
G
) have a tolerance and temperature drift different
than the external resistor, the absolute gain accuracy
and gain drift over temperature will be relatively poor
compared to the previously described standard gain
connections using no external resistor.
OUTPUT CURRENT AND VOLTAGES
The OPA832 provides outstanding output voltage cap-
ability. For the +5V supply, under no-load conditions at
+25°C, the output voltage typically swings closer than
60mV to either supply rail.
The minimum specified output voltage and current
specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at
cold startup will the output current and voltage decrease
to the numbers shown in the min/max tables. As the out-
put transistors deliver power, their junction tempera-
tures will increase, decreasing their V
BE
s (increasing
the available output voltage swing) and increasing their
current gains (increasing the available output current).
In steady-state operation, the available output voltage
and current will always be greater than that shown in the
over-temperature specifications, since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normal-
ly be a problem, since most applications include a series
matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is
shorted to ground. However, shorting the output pin di-
rectly to the adjacent positive power-supply pin (8-pin
packages) will possibly destroy the amplifier. If addition-
al short-circuit protection is required, consider a small
series resistor in the power-supply leads. This will re-
duce the available output voltage swing under heavy
output loads.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often,
the capacitive load is the input of an ADC—including
additional external capacitance which may be recom-
mended to improve ADC linearity. A high-speed, high