Datasheet

"#$
SBOS263F − AUGUST 2004 − REVISED AUGUST 2008
www.ti.com
20
OPA830
+5V
−
5V
V
O
50
Ω
V
IN
R
F
750
Ω
348
Ω
50
Ω
Source
150
Ω
R
G
750
Ω
6.8
µ
F
+
6.8
µ
F
+
0.1
µ
F
0.1
µ
F
0.01
µ
F
Figure 3. DC-Coupled, G = +2, Bipolar Supply
Specification and Test Circuit
SINGLE-SUPPLY ADC INTERFACE
The ADC interface on the front page shows a DC-coupled,
single-supply ADC driver circuit. Many systems are now
requiring +3V supply capability of both the ADC and its
driver. The OPA830 provides excellent performance in this
demanding application. Its large input and output voltage
ranges and low distortion support converters such as the
THS1040 shown in the figure on page 1. The input
level-shifting circuitry was designed so that V
IN
can be
between 0V and 0.5V, while delivering an output voltage
of 1V to 2V for the THS1040.
DC LEVEL-SHIFTING
Figure 4 shows a DC-coupled noninverting amplifier that
level-shifts the input up to accommodate the desired
output voltage range. Given the desired signal gain (G),
and the amount V
OUT
needs to be shifted up (∆V
OUT
)
when V
IN
is at the center of its range, the following
equations give the resistor values that produce the desired
performance. Assume that R
4
is between 200Ω and
1.5kΩ.
NG = G + V
OUT
/V
S
R
1
= R
4
/G
R
2
= R
4
/(NG − G)
R
3
= R
4
/(NG −1)
where:
NG = 1 + R
4
/R
3
V
OUT
= (G)V
IN
+ (NG − G)V
S
Make sure that V
IN
and V
OUT
stay within the specified
input and output voltage ranges.
OPA830
+V
S
V
OUT
V
IN
R
3
R
2
R
1
R
4
Figure 4. DC Level-Shifting
The circuit on the front page is a good example of this type
of application. It was designed to take V
IN
between 0V and
0.5V and produce V
OUT
between 1V and 2V when using
a +3V supply. This means G = 2.00, and
∆V
OUT
= 1.50V − G × 0.25V = 1.00V. Plugging these
values into the above equations (with R
4
= 750Ω) gives:
NG = 2.33, R
1
= 375Ω, R
2
= 2.25kΩ, and R
3
= 563Ω. The
resistors were changed to the nearest standard values for
the front page circuit.
AC-COUPLED OUTPUT VIDEO LINE DRIVER
Low-power and low-cost video line drivers often buffer
digital-to-analog converter (DAC) outputs with a gain of 2
into a doubly-terminated line. Those interfaces typically
require a DC blocking capacitor. For a simple solution, that
interface often has used a very large value blocking
capacitor (220µF) to limit tilt, or SAG, across the frames.
One approach to creating a very low high-pass pole
location using much lower capacitor values is shown in
Figure 5. This circuit gives a voltage gain of 2 at the output
pin with a high-pass pole at 8Hz. Given the 150Ω load, a
simple blocking capacitor approach would require a 133µF
value. The two much lower valued capacitors give this
same low-pass pole using this simple SAG correction
circuit of Figure 5.