Datasheet

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SBOS303C − JUNE 2004 − REVISED AUGUST 2008
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20
NOISE PERFORMANCE
The OPA820 complements its low harmonic distortion with low
input noise terms. Both the input-referred voltage noise and
the two input-referred current noise terms combine to give a
low output noise under a wide variety of operating conditions.
Figure 12 shows the op amp noise analysis model with all the
noise terms included. In this model, all the noise terms are
taken to be noise voltage or current density terms in either
nV/√Hz
or pA/√Hz.
4kT
R
G
R
G
R
F
R
S
OPA820
I
BI
E
O
I
BN
4kT = 1.6E
−
20J
at 290
_
K
E
RS
E
NI
√
4kTR
S
√
4kTR
F
Figure 12. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as the square
root of the squared contributing terms to the output noise
voltage. This computation is adding all the contributing noise
powers at the output by superposition, then taking the square
root to get back to a spot noise voltage. Equation 7 shows the
general form for this output noise voltage using the terms
presented in Figure 12.
E
O
+
ƪ
E
2
NI
)
ǒ
I
BN
R
S
Ǔ
2
) 4kTR
S
ƫ
NG
2
)
ǒ
I
BI
R
F
Ǔ
2
) 4kTR
F
NG
Ǹ
Dividing this expression by the noise gain (NG = 1 + R
F
/R
G
)
will give the equivalent input referred spot noise voltage at the
noninverting input, as shown in Equation 8.
E
N
+ E
2
NI
)
ǒ
I
BN
R
S
Ǔ
2
) 4kTR
S
)
ǒ
I
BI
R
F
NG
Ǔ
2
)
4kTR
F
NG
Ǹ
Evaluating these two equations for the OPA820 circuit
presented in Figure 1 will give a total output spot noise voltage
of 6.44nV/√Hz
and an equivalent input spot noise voltage of
3.22nV/√Hz
.
DC OFFSET CONTROL
The OPA820 can provide excellent DC signal accuracy
because of its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset
voltage and bias current offset errors. To take full advantage
of this low input offset voltage, careful attention to input bias
current cancellation is also required. The high-speed input
stage for the OPA820 has a moderately high input bias current
(9µA typ into the pins) but with a very close match between the
two input currents—typically 100nA input offset current. The
total output offset voltage may be considerably reduced by
matching the source impedances looking out of the two inputs.
For example, one way to add bias current cancellation to the
circuit of Figure 1 would be to insert a 175Ω series resistor into
the noninverting input from the 50Ω terminating resistor. When
the 50Ω source resistor is DC-coupled, this will increase the
source impedance for the noninverting input bias current to
200Ω. Since this is now equal to the impedance looking out of
the inverting input (R
F
|| R
G
), the circuit will cancel the gains for
the bias currents to the output leaving only the offset current
times the feedback resistor as a residual DC error term at the
output. Using a 402Ω feedback resistor, this output error will
now be less than ±0.4µA × 402Ω = ±160µV at 25°C.
THERMAL ANALYSIS
The OPA820 will not require heatsinking or airflow in most
applications. Maximum desired junction temperature would
set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed +150°C.
Operating junction temperature (T
J
) is given by
T
A
+P
D
× q
JA
. The total internal power dissipation (P
D
) is the
sum of quiescent power (P
DQ
) and additional power
dissipated in the output stage (P
DL
) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. P
DL
will
depend on the required output signal and load but would, for
a grounded resistive load, be at a maximum when the output
is fixed at a voltage equal to 1/2 of either supply voltage (for
equal bipolar supplies). Under this worst-case condition,
P
DL
= V
S
2
/(4 × R
L
), where R
L
includes feedback network
loading.
Note that it is the power in the output stage and not in the load
that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA820IDBV (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C.
P
D
= 10V(6.4mA) + 5
2
/(4 × (100Ω || 800Ω)) = 134mW
Maximum T
J
= +85°C + (134mW × 150°C/W) = 105°C
BOARD LAYOUT
Achieving optimum performance with a high-frequency
amplifier such as the OPA820 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
unbroken elsewhere on the board.
(7)
(8)