Datasheet

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SBOS303C − JUNE 2004 − REVISED AUGUST 2008
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15
BUFFERING HIGH-PERFORMANCE ADCs
To achieve full performance from a high dynamic range ADC,
considerable care must be exercised in the design of the input
amplifier interface circuit. The example circuit on the front
page shows a typical AC-coupled interface to a very high
dynamic range converter. This AC-coupled example allows
the OPA820 to be operated using a signal range that swings
symmetrically around ground (0V). The 2V
PP
swing is then
level-shifted through the blocking capacitor to a midscale
reference level, which is created by a well-decoupled resistive
divider off the converter’s internal reference voltages. To have
a negligible effect (1dB) on the rated spurious-free dynamic
range (SFDR) of the converter, the amplifier’s SFDR should be
at least 18dB greater than the converter. The OPA820 has
minimal effect on the rated distortion of the ADS850, given its
79dB SFDR at 2V
PP
, 1MHz. The > 90dB (< 1MHz) SFDR for
the OPA820 in this configuration implies a < 3dB degradation
(for the system) from the converter’s specification. For further
SFDR improvement with the OPA820, a differential
configuration is suggested.
Successful application of the OPA820 for ADC driving
requires careful selection of the series resistor at the amplifier
output, along with the additional shunt capacitor at the ADC
input. To some extent, selection of this RC network will be
determined empirically for each converter. Many high-
performance CMOS ADCs, such as the ADS850, perform
better with the shunt capacitor at the input pin. This capacitor
provides low source impedance for the transient currents
produced by the sampling process. Improved SFDR is often
obtained by adding this external capacitor, whose value is
often recommended in this converter data sheet. The external
capacitor, in combination with the built-in capacitance of the
ADC input, presents a significant capacitive load to the
OPA820. Without a series isolation resistor, an undesirable
peaking or loss of stability in the amplifier may result.
Since the DC bias current of the CMOS ADC input is
negligible, the resistor has no effect on overall gain or offset
accuracy. Refer to the typical characteristic R
S
vs Capacitive
Load to obtain a good starting value for the series resistor. This
will ensure flat frequency response to the ADC input.
Increasing the external capacitor value will allow the series
resistor to be reduced. Intentionally bandlimiting using this RC
network can also be used to limit noise at the converter input.
VIDEO LINE DRIVING
Most video distribution systems are designed with 75Ω series
resistors to drive a matched 75Ω cable. In order to deliver a net
gain of 1 to the 75Ω matched load, the amplifier is typically set
up for a voltage gain of +2, compensating for the 6dB
attenuation of the voltage divider formed by the series and
shunt 75Ω resistors at either end of the cable.
The circuit of Figure 1 applies to this requirement if all
references to 50Ω resistors are replaced by 75Ω values.
Often, the amplifier gain is further increased to 2.2, which
recovers the additional DC loss of a typical long cable run. This
change would require the gain resistor (R
G
) in Figure 1 to be
reduced from 402Ω to 335Ω. In either case, both the gain
flatness and the differential gain/phase performance of the
OPA820 will provide exceptional results in video distribution
applications. Differential gain and phase measure the change
in overall small-signal gain and phase for the color sub-carrier
frequency (3.58MHz in NTSC systems) versus changes in the
large-signal output level (which represents luminance
information in a composite video signal). The OPA820, with
the typical 150Ω load of a single matched video cable, shows
less than 0.01%/0.01° differential gain/phase errors over the
standard luminance range for a positive video (negative sync)
signal. Similar performance would be observed for multiple
video signals, as shown in Figure 5.
OPA820
V
OUT
402
Ω
335
Ω
Video
Input
75
Ω
75
Ω
75
Ω
Transmission Line
V
OUT
75
Ω
75
Ω
V
OUT
75
Ω
75
Ω
75
Ω
High output current drive capability allows three
back−terminated 75
Ω
transmission lines to be simultaneously driven.
Figure 5. Video Distribution Amplifier