Datasheet

OPA695
27
SBOS293G
www.ti.com
somewhat higher and are unmatched. Although bias current
cancellation techniques are very effective with most voltage-
feedback op amps, they do not generally reduce the output
DC offset for wideband current-feedback op amps. Since the
two input bias currents are unrelated in both magnitude and
polarity, matching the source impedance looking out of each
input to reduce their error contribution to the output is
ineffective. Evaluating the configuration of Figure 1, using a
worst-case +25°C input offset voltage and the two input bias
currents, gives a worst-case output offset range equal to:
±(NG • V
OS
) + (I
BN
• R
S
/2 • NG) ±(I
BI
• R
F
)
where NG = non-inverting signal gain
= ±(8 • 3.0mV) ± (30µA • 25Ω • 8) ±(402Ω • 60µA)
= ±24mV ± 1.6mV ±24mV
= ±54mV
A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
simple adjustment techniques do not correct for temperature
drift.
POWER SHUTDOWN OPERATION
The OPA695 provides an optional power shutdown feature
that can be used to reduce system power. If the V
DIS
control
pin is left unconnected, the OPA695 operates normally. This
shutdown is intended only as a power-saving feature. For-
ward path isolation is very good for small signals. Large
signal isolation is not ensured. Using this feature to multiplex
two or more outputs together is not recommended. Large
signals applied to the shutdown output stages can turn on
parasitic devices, degrading signal linearity for the desired
channel.
Turn-on time is very quick from the shutdown condition,
typically < 60ns. Turn-off time is strongly dependent on the
external circuit configuration, but is typically 200ns for the
circuit of Figure 1.
To shut down, the control pin must be asserted low. This
logic control is referenced to the positive supply, as shown in
the simplified circuit of Figure 18.
In normal operation, base current to Q1 is provided through
the 120kΩ resistor, while the emitter current through the 8kΩ
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1’s emitter. As V
DIS
is pulled low,
additional current is pulled through the 8kΩ resistor, eventu-
ally turning on these two diodes (≈ 180µA). At this point, any
further current pulled out of V
DIS
goes through those diodes
holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply current in the shutdown mode is only
that required to operate the circuit of Figure 18.
When disabled, the output and input nodes go to a high
impedance state. If the OPA695 is operating in a gain of +1,
this will show a very high impedance (3pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a gain
greater than +1, the total feedback network resistance (R
F
+
R
G
) will appear as the impedance looking back into the
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (R
F
+ R
G
), giving relatively poor input to
output isolation.
THERMAL ANALYSIS
The OPA695 does not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 150°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
• θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
will depend on the
required output signal and load. However, for a grounded
resistive load, P
DL
would be at a maximum when the
output is fixed at a voltage equal to one-half of either supply
voltage (for equal bipolar supplies). Under this condition,
P
DL
= V
S
2
/(4 • R
L
), where R
L
includes feedback network
loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
T
J
using an OPA695IDBV (SOT23-6 package) in the circuit
of Figure 1 operating at the maximum specified ambient
temperature of +85°C and driving a grounded 100Ω load.
P
D
= 10V • 14.1mA + 5
2
/(4 • (100Ω || 458Ω)) = 217mW
Maximum T
J
= +85°C + (0.22W • 150°C/W) = 118°C
This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
since an absolute worst-case output stage power was as-
sumed in this calculation.
FIGURE 18. Op Amp Noise Figure Analysis Model.
17kΩ
120kΩ
8kΩ
I
S
Control
–V
S
+V
S
V
DIS
Q1