Datasheet

OPA694
www.ti.com SBOS319G –SEPTEMBER 2004–REVISED JANUARY 2010
requirement for the circuit in Figure 41. Perfect BOARD LAYOUT GUIDELINES
cancellation over process and temperature is not
Achieving optimum performance with a
possible. However, this initial resistor setting and
high-frequency amplifier like the OPA694 requires
precise gain matching will minimize long-term pulse
careful attention to board layout parasitics and
settling tails.
external component types. Recommendations that
will optimize performance include:
THERMAL ANALYSIS
a) Minimize parasitic capacitance to any AC ground
Due to the high output power capability of the
for all of the signal I/O pins. Parasitic capacitance on
OPA694, heatsinking or forced airflow may be
the output and inverting input pins can cause
required under extreme operating conditions.
instability: on the noninverting input, it can react with
Maximum desired junction temperature will set the
the source impedance to cause unintentional
maximum allowed internal power dissipation, as
bandlimiting. To reduce unwanted capacitance, a
described below. In no case should the maximum
window around the signal I/O pins should be opened
junction temperature be allowed to exceed +150°C.
in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be
Operating junction temperature (T
J
) is given by T
A
+
unbroken elsewhere on the board.
P
D
× q
JA
. The total internal power dissipation (P
D
) is
the sum of quiescent power (P
DQ
) and additional
b) Minimize the distance (< 0.25in, or 0.635cm)
power dissipated in the output stage (P
DL
) to deliver
from the power-supply pins to high-frequency 0.1mF
load power. Quiescent power is simply the specified
decoupling capacitors. At the device pins, the ground
no-load supply current times the total supply voltage
and power plane layout should not be in close
across the part. P
DL
will depend on the required
proximity to the signal I/O pins. Avoid narrow power
output signal and load but would, for a grounded
and ground traces to minimize inductance between
resistive load, be at a maximum when the output is
the pins and the decoupling capacitors. The
fixed at a voltage equal to 1/2 either supply voltage
power-supply connections (on pins 4 and 7) should
(for equal bipolar supplies). Under this condition P
DL
always be decoupled with these capacitors. An
= V
S
2
/(4 × R
L
) where R
L
includes feedback network
optional supply decoupling capacitor across the two
loading.
power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2mF
Note that it is the power in the output stage and not in
to 6.8mF) decoupling capacitors, effective at lower
the load that determines internal power dissipation.
frequencies, should also be used on the main supply
As a worst-case example, compute the maximum T
J
pins. These may be placed somewhat farther from
using an OPA694IDBV (SOT23-5 package) in the
the device and may be shared among several
circuit of Figure 31 operating at the maximum
devices in the same area of the PCB.
specified ambient temperature of +85°C and driving a
c) Careful selection and placement of external
grounded 20Ω load to +2.5V DC:
components will preserve the high-frequency
P
D
= 10V × 6.0mA + 5
2
/[4 × (20Ω || 804Ω)] = 380mΩ
performance of the OPA694. Resistors should be a
very low reactance type. Surface-mount resistors
Maximum T
J
= +85°C + (0.38W × (150°C/W) = 142°C
work best and allow a tighter overall layout. Metal-film
Although this is still below the specified maximum
and carbon composition, axially-leaded resistors can
junction temperature, system reliability considerations
also provide good high-frequency performance.
may require lower junction temperatures. Remember,
Again, keep their leads and PCB trace length as short
this is a worst-case internal power dissipation—use
as possible. Never use wirewound type resistors in a
your actual signal and load to compute P
DL
. The
high-frequency application. Since the output pin and
highest possible internal dissipation will occur if the
inverting input pin are the most sensitive to parasitic
load requires current to be forced into the output for
capacitance, always position the feedback and series
positive output voltages or sourced from the output
output resistor, if any, as close as possible to the
for negative output voltages. This puts a high current
output pin. Other network components, such as
through a large internal voltage drop in the output
noninverting input termination resistors, should also
transistors. The Output Voltage and Current
be placed close to the package. Where double-side
Limitations plot (Figure 21) shown in the Typical
component mounting is allowed, place the feedback
Characteristics includes a boundary for 1W maximum
resistor directly under the package on the other side
internal power dissipation under these conditions.
of the board between the output and inverting input
pins. The frequency response is primarily determined
space
by the feedback resistor value, as described
space
previously. Increasing its value will reduce the
bandwidth, while decreasing it will give a more
space
peaked frequency response. The 402Ω feedback
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