Datasheet

OPA693
16
SBOS285A
www.ti.com
SINGLE-SUPPLY ADC INTERFACE
Most modern, high-performance ADCs (such as the Texas
Instruments ADS8xx series) operate on a single +5V (or
lower) power supply. It has been a considerable challenge
for single-supply op amps to deliver a low distortion input
signal at the ADC input for signal frequencies exceeding
5MHz. The high slew rate, exceptional output swing, and
high linearity of the OPA693 make it an ideal single-supply
ADC driver. Figure 6 shows an example input interface to a
very high-performance, 10-bit, 75MSPS CMOS converter.
The OPA693 in the circuit of Figure 6 provides > 500MHz
bandwidth at an operating gain of +2V/V delivering 1V
PP
at the
output for a 0.5V
PP
input. This broad bandwidth provides
adequate margin to deliver low distortion to the maximum
20Mhz analog input frequency intended for the circuit of Figure
6. A 40MHz low-pass filter is provided as part of the converter
interface to both limit broadband noise and reduce harmonics
as the signal frequency exceeds 15MHz. The noninverting input
bias voltage is referenced to the midpoint of the ADC signal
range by dividing off the top and bottom of the internal ADC
reference ladder.
WIDEBAND UNITY GAIN BUFFER WITH IMPROVED
FLATNESS
As shown in the Typical Characteristic curves, the unity gain
buffer configuration of Figure 2 shows a peaking in the fre-
quency response exceeding 2dB. This gives the slight amount
of overshoot and ringing apparent in the gain of +1V/V pulse
response curves. A similar circuit that holds a flatter frequency
response, giving improved pulse fidelity, is shown in Figure 7.
This circuit removes the peaking by bootstrapping out any
parasitic effects on R
G
. The input impedance is still set by R
M
as the apparent impedance looking into R
G
is very high. R
M
may be increased to show a higher input impedance, but
larger values will start to impact DC output offset voltage.
Figure 6. Wideband, AC-Coupled, Single-Supply ADC Driver.
OPA693
300Ω
+2.5V DC Bias
ADS828
10-Bit
75MSPS
50Ω
1V
PP
DIS
100pF
Input
300Ω
REFB
REFT
CM
Input
1000pF
1000pF
0.5V
PP
2kΩ
0.1µF
+3.5V
2kΩ
0.1µF
+1.5V
+5V
Clock
+5V
R
G
R
F
Figure 7. Improved Unity Gain Buffer.
OPA693
+5V
DIS
R
O
50Ω
V
O
R
F
300Ω
R
G
300Ω
R
M
50Ω
−5V
V
I
Figure 8. Buffer Frequency Response Comparison.
2
1
0
−1
−2
−3
−4
−5
−6
Normalized Gain (dB)
10 100 1000
Frequency (MHz)
G = +1, Figure 2
G = +1, Figure 7
This circuit creates an additional input offset voltage as the
difference in the two input bias currents times the impedance
to ground at V
I
. Figure 8 shows a comparison of small-signal
frequency response for the unity gain buffer of Figure 2
compared to the improved approach shown in Figure 7.