Datasheet

OPA692
2
SBOS236E
www.ti.com
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
OPA692ID SO-8 Surface-Mount D –40°C to +85°C OPA692 OPA692ID Rails, 100
"""""OPA692IDR Tape and Reel, 2500
OPA692IDBV SOT23-6 DBV –40°C to +85°C OAGI OPA692IDBVT Tape and Reel, 250
"""""OPA692IDBVR Tape and Reel, 3000
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply ............................................................................... ±6.5V
DC
Internal Power Dissipation
(2)
............................ See Thermal Information
Differential Input Voltage
(3)
............................................................... ±1.2V
Input Voltage Range............................................................................ ±V
S
Storage Temperature Range: D, DVB ...........................–65°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (T
J
) ........................................................... +175°C
ESD Resistance: HBM ........................................................................ 2kV
MM ........................................................................ 200V
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
(2) Packages must be derated based on specified
θ
JA
. Maximum T
J
must be
observed. (3) Noninverting input to internal inverting node.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PIN CONFIGURATION
Top View SO Top View SOT
PACKAGE/ORDERING INFORMATION
(1)
1
2
3
4
8
7
6
5
DIS
+V
S
Output
NC
R
F
402Ω
R
G
402Ω
NC
–IN
+IN
–V
S
NC: No Connection
1
2
3
6
5
4
Output
–V
S
+IN
+V
S
DIS
–IN
R
F
402Ω
R
G
402Ω
123
654
OAGI
Pin Orientation/Package Marking
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.