Datasheet

OPA692
19
SBOS236E
www.ti.com
unconnected, the OPA692 will operate normally. To disable,
the control pin must be asserted LOW. Figure 9 shows a
simplified internal circuit for the disable control feature.
THERMAL ANALYSIS
Due to the high output power capability of the OPA692,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation, as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
• θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
depends on the required
output signal and load but would, for a grounded resistive
load, be at a maximum when the output is fixed at a voltage
equal to 1/2 either supply voltage (for equal bipolar supplies).
Under this condition P
DL
= V
S
2
/(4 • R
L
), where R
L
includes
feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA692IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 20Ω load to +2.5V
DC
:
P
D
= 10V • 5.8mA + 5
2
/(4 • (20Ω || 800Ω)) = 378mW
Maximum T
J
= +85°C + (0.39W • 150°C/W) = 142°C
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower junction temperatures. Remember, this is a
worst-case internal power dissipation—use your actual sig-
nal and load to compute P
DL
. The highest possible internal
dissipation occurs if the load requires current to be forced
into the output for positive output voltages or sourced from
the output for negative output voltages. This puts a high
current through a large internal voltage drop in the output
transistors. The “Output Voltage and Current Limitations” plot
shown in the Typical Characteristics include a boundary for
1W maximum internal power dissipation under these condi-
tions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency am-
plifier like the OPA692 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output pin can cause instability: on the noninverting input, it
can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the 15kΩ
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1’s emitter. As V
DIS
is pulled LOW,
additional current is pulled through the 15kΩ resistor eventu-
ally turning on these two diodes (≈ 75µA). At this point, any
further current pulled out of V
DIS
goes through those diodes
holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply current in the disable mode is only
that required to operate the circuit of Figure 8. Additional
circuitry ensures that turn-on time occurs faster than turn-off
time (make-before-break).
When disabled, the output and input nodes go to a high-
impedance state. If the OPA692 is operating in a gain of +1,
this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a gain
of +2, the total feedback network resistance (R
F
+ R
G
) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured at a gain of –1, the input and output
will be connected through the feedback network resistance
(R
F
+ R
G
) giving relatively poor input to output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. The Typical
Characteristics show these glitches for the circuit of Figure 1
with the input signal set to 0V. The glitch waveform at the
output pin is plotted along with the
DIS pin voltage.
The transition edge rate (dV/dt) of the
DIS control line will
influence this glitch. Slowing this edge can be achieved by
adding a simple RC filter into the V
DIS
pin from a higher
speed logic line. If extremely fast transition logic is used, a
2kΩ series resistor between the logic gate and the
DIS input
pin will provide adequate bandlimiting using just the parasitic
input capacitance on the
DIS pin while still ensuring an
adequate logic level swing.
25kΩ
110kΩ
15kΩ
I
S
Control
–V
S
+V
S
V
DIS
Q1
FIGURE 9. Simplified Disable Control Circuit.