Datasheet

OPA691
20
SBOS226D
www.ti.com
THERMAL ANALYSIS
Due to the high output power capability of the OPA691,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation, as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
• θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P
DL
= V
S
2
/(4 • R
L
) where R
L
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA691IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 20Ω load to +2.5V DC:
P
D
= 10V • 5.7mA + 5
2
/(4 • (20Ω || 804Ω)) = 377mΩ
Maximum T
J
= +85°C + (0.377W • (150°C/W) = 141.5°C
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower junction temperatures. Remember, this is a
worst-case internal power dissipation—use your actual sig-
nal and load to computer P
DL
. The highest possible internal
dissipation will occur if the load requires current to be forced
into the output for positive output voltages or sourced from
the output for negative output voltages. This puts a high
current through a large internal voltage drop in the output
transistors. The “Output Voltage and Current Limitations” plot
shown in the Typical Characteristics includes a boundary for
1W maximum internal power dissipation under these condi-
tions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency am-
plifier like the OPA691 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling capaci-
tor across the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower frequen-
cies, should also be used on the main supply pins. These
may be placed somewhat farther from the device and may be
shared among several devices in the same area of the PC
board.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA691. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal-film and carbon composition, axially-leaded
resistors can also provide good high-frequency performance.
Again, keep their leads and PC board trace length as short
as possible. Never use wirewound type resistors in a high-
frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. The
frequency response is primarily determined by the feedback
resistor value as described previously. Increasing its value
will reduce the bandwidth, while decreasing it will give a more
peaked frequency response. The 402Ω feedback resistor
used in the Electrical Characteristic tables at a gain of +2 on
±5V supplies is a good starting point for design. Note that a
453Ω feedback resistor, rather than a direct short, is recom-
mended for the unity-gain follower application. A current
feedback op amp requires a feedback resistor even in the
unity-gain follower configuration to control stability.
d) Connections to other wideband devices on the board
may be made with short, direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
plot of recommended R
S
versus Capacitive Load. Low para-
sitic capacitive loads (< 5pF) may not need an R
S
since the
OPA691 is nominally compensated to operate with a 2pF
parasitic load. If a long trace is required, and the 6dB signal
loss intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an ECL