Datasheet

OPA691
12
SBOS226D
www.ti.com
SINGLE-SUPPLY ADC INTERFACE
Most modern, high performance ADCs (such as the Texas
Instruments ADS8xx and ADS9xx series) operate on a single
+5V (or lower) power supply. It has been a considerable
challenge for single-supply op amps to deliver a low distor-
tion input signal at the ADC input for signal frequencies
exceeding 5MHz. The high slew rate, exceptional output
swing, and high linearity of the OPA691 make it an ideal
single-supply ADC driver. Figure 3 shows an example input
interface to a very high performance, 10-bit, 60MSPS CMOS
converter.
The OPA691 in the circuit of Figure 3 provides > 180MHz
bandwidth operating at a signal gain of +4 with a 2V
PP
output
swing. One of the primary advantages of the current feed-
back internal architecture used in the OPA691 is that high
bandwidth can be maintained as the signal gain is increased.
The noninverting input bias voltage is referenced to the
midpoint of the ADC signal range by dividing off the top and
bottom of the internal ADC reference ladder. With the gain
resistor (R
G
) AC-coupled, this bias voltage has a gain of +1
to the output, centering the output voltage swing as well.
Tested performance at a 20MHz analog input frequency and
a 60MSPS clock rate on the converter gives > 58dBc SFDR.
WIDEBAND INVERTING SUMMING AMPLIFIER
Since the signal bandwidth for a current feedback op amp may
be controlled independently of the noise gain (NG, which is
normally the same as the noninverting signal gain), very
broadband inverting summing stages may be implemented
using the OPA691. The circuit on the front page of this data
sheet shows an example inverting summing amplifier where
the resistor values have been adjusted to maintain both
maximum bandwidth and input impedance matching. If each
RF signal is assumed to be driven from a 50Ω source, the NG
for this circuit will be (1 + 100Ω/(100Ω/5)) = 6. The total
feedback impedance (from V
O
to the inverting error current) is
the sum of R
F
+ (R
I
• NG) where R
I
is the impedance looking
into the inverting input from the summing junction (see the
Setting Resistor Values to Optimize Performance section).
Using 100Ω feedback (to get a signal gain of –2 from each
input to the output pin) requires an additional 30Ω in series
with the inverting input to increase the feedback impedance.
With this resistor added to the typical internal R
I
= 35Ω, the
total feedback impedance is 100Ω + (65Ω • 6) = 490Ω, which
is equal to the required value to get a maximum bandwidth flat
frequency response for NG = 6. Tested performance shows
more than 200MHz small-signal bandwidth and a –1dBm
compression of 15dBm at the matched 50Ω load through
100MHz.
WIDEBAND VIDEO MULTIPLEXING
One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple “Wired-OR
Video Multiplexer” can be easily implemented using the
OPA691, see Figure 4.
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approxi-
mately equal at this time. The “make-before-break” disable
characteristic of the OPA691 ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that presented in Figure 4. Since both inputs may
be on for a short period during the transition between
channels, the outputs are combined through the output
impedance matching resistors (82.5Ω in this case). When
one channel is disabled, its feedback network forms part of
the output impedance and slightly attenuates the signal in
getting out onto the cable. The gain and output matching
resistor have been slightly increased to get a signal gain of
+1 at the matched load and provide a 75Ω output impedance
to the cable. The video multiplexer connection (see Figure 4)
FIGURE 3. Wideband, AC-Coupled, Single-Supply ADC Driver.
OPA691
360Ω
+2.5V DC Bias
ADS823
10-Bit
60MSPS
50Ω
2Vp-p
DIS
22pF
Input
120Ω
REFB
REFT
CM
Input
0.1µF
0.1µF
0.5Vp-p
2kΩ
0.1µF
+3.5V
2kΩ
0.1µF
+1.5V
+5V
Clock
+5V
R
G
R
F