Datasheet

OPA684
20
SBOS219D
www.ti.com
The OPA684 provides very high power gain on low quiescent
current levels. When disabled, internal high impedance nodes
discharge slowly that, with the exceptional power gain pro-
vided, give a self-powering characteristic that leads to a slow
turn-off characteristic. Typical turn-off times to rated 100µA
disabled supply current are 4ms. Turn-on times are very
fast—less than 40ns.
THERMAL ANALYSIS
The OPA684 will not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
• θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition P
DL
= V
S
2
/(4 • R
L
),
where R
L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
T
J
using an OPA684IDBV (SOT23-6 package) in the circuit
of Figure 1 operating at the maximum specified ambient
temperature of +85°C and driving a grounded 100Ω load.
P
D
= 10V • 1.85mA + 5
2
/(4 • (100Ω || 2kΩ)) = 84mW
Maximum T
J
= +85°C + (0.084W • 150°C/W) = 98°C.
This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst-case output stage power
was assumed in this calculation.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency am-
plifier like the OPA684 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the non-inverting input, it can react with the source
impedance to cause unintentional bandlimiting. To re-
duce unwanted capacitance, a window around the sig-
nal I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capaci-
tors. The power-supply connections should always be
decoupled with these capacitors. An optional supply de-
coupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling ca-
pacitors, effective at lower frequencies, should also be
used on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PC
board.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance
of the OPA684. Resistors should be a very low reac-
tance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composi-
tion axially-leaded resistors can also provide good high-
frequency performance. Again, keep their leads and PC
board trace length as short as possible. Never use
wirewound type resistors in a high-frequency applica-
tion. Since the output pin and inverting input pin are the
most sensitive to parasitic capacitance, always position
the feedback and series output resistors, if any, as close
as possible to the output pin. Other network compo-
nents, such as non-inverting input termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place the
feedback resistor directly under the package on the
other side of the board between the output and inverting
input pins. The frequency response is primarily deter-
mined by the feedback resistor value, as described
previously. Increasing its value will reduce the peaking
at higher gains, while decreasing it will give a more
peaked frequency response at lower gains. The 1kΩ
feedback resistor used in the electrical characteristics at
a gain of +2 on ±5V supplies is a good starting point for
design. Note that a 1kΩ feedback resistor, rather than a
direct short, is required for the unity-gain follower appli-
cation. A current-feedback op amp requires a feedback
resistor even in the unity gain follower configuration to
control stability.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-
board transmission lines. For short connections, con-
sider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the
total capacitive load and set R
S
from the plot of recom-
mended
R
S
vs C
LOAD
. Low parasitic capacitive loads
(< 5pF) may not need an R
S
since the OPA684 is