Datasheet

OPA684
17
SBOS219D
www.ti.com
going over a 50:1 gain range gives only a factor of 3.5
bandwidth reduction. The 50MHz bandwidth at a gain of
100V/V is equivalent to a 5GHz gain-bandwidth product
voltage-feedback amplifier capability.
OUTPUT CURRENT AND VOLTAGE
The OPA684 provides output voltage and current capabilities
that can support the needs of driving doubly-terminated 50Ω
lines. For a 100Ω load at the gain of +2, (see Figure 1), the total
load is the parallel combination of the 100Ω load and the 2kΩ
total feedback network impedance. This 95Ω load will require
no more than 40mA output current to support the ±3.8V
minimum output voltage swing for 100Ω loads. This is well
under the specified minimum +130/–100mA specifications
over the full temperature range.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
Output Current and Voltage Limitations curve in the Typical
Characteristics. The X and Y axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA684’s output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures will increase, de-
creasing their V
BE
s (increasing the available output voltage
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the avail-
able output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To maintain maximum output stage linearity, no output short-
circuit protection is provided. Normally, this will not be a
problem since most applications include a series-matching
resistor at the output that will limit the internal power dissipa-
tion if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin (8-pin packages) will, in most
cases, destroy the amplifier. If additional short-circuit protec-
tion is required, consider a small-series resistor in the power-
supply leads. This will, under heavy output loads, reduce the
available output voltage swing. A 5Ω series resistor in each
power-supply lead will limit the internal power dissipation to
less than 1W for an output short-circuit, while decreasing the
available output voltage swing only 0.25V for up to 50mA
desired load currents. Always place the 0.1µF power-supply
decoupling capacitors after these supply current limiting
resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an Analog-to-Digital Converter
(ADC), including additional external capacitance which may
be recommended to improve ADC linearity. A high-speed,
high open-loop gain, amplifier like the OPA684 can be very
susceptible to decreased stability and closed-loop response
peaking when a capacitive load is placed directly on the
output pin. When the amplifier’s open-loop output resistance
is considered, this capacitive load introduces an additional
pole in the signal path that can decrease the phase margin.
Several external solutions to this problem have been sug-
gested. When the primary considerations are frequency
response flatness, pulse response fidelity, and/or distortion,
the simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the ca-
pacitive load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
2000
1750
1500
1250
1000
750
500
Voltage Gain (V/V)
2 5 10 20 50 100
BANDWIDTH AND R
F
OPTIMIZED vs GAIN
Feedback Resistor (Ω)
200
150
100
50
Bandwidth (MHz)
Bandwidth
Right Scale
R
F
Left Scale
3
0
–3
–6
–9
–1.2
Frequency (MHz)
10 100 200
SMALL-SIGNAL RESPONSE WITH OPTIMIZED R
F
Normalized Gain (dB)
G = 100
G = 50
G = 5
G = 2
G = 10
G = 20
FIGURE 11. Bandwidth and R
F
Optimized vs Gain.
FIGURE 12. Small-Signal Frequency Response with Opti-
mized R
F
.