Datasheet

OPA657
15
SBOS197E
www.ti.com
impedances > 750k. This would also be the feedback resistor
value for transimpedance applications (Figure 3) where the
output DC error due to inverting input bias current is on the order
of that contributed by the input offset voltage. In general, except
for these extremely high-impedance values, the output DC errors
due to the input bias current may be neglected.
After the input offset voltage itself, the most significant term
contributing to output offset voltage is the PSRR for the negative
supply. This term is modeled as an input offset voltage shift due
to changes in the negative power supply voltage (and similarly for
the +PSRR). The high-grade test limit for PSRR is 68dB. This
translates into 0.40mV/V input offset voltage shift = 10
(68/20)
. This
low sensitivity to the negative supply voltage would require a 1.5V
change in the negative supply to match the ±0.6mV input offset
voltage error. The +PSRR is tested to a minimum value of 78dB.
This translates into 10
(78/20)
= 0.125mV/V sensitivity for the input
offset voltage to positive power-supply changes.
As an example, compute the worst-case output DC error for the
transimpedance circuit of Figure 3 at 25°C and then the shift
over the 0°C to 70°C range given the following assumptions.
Negative Power Supply
= 5V ±0.2V with a ±5mV/°C worst-case shift
Positive Power Supply
= +5V ±0.2V with a ±5mV/°C worst-case shift
Initial 25°C Output DC Error Band
= ±0.6mV (OPA657 high-grade input offset voltage limit)
±0.08mV (due to the PSRR = 0.4mV/V ±0.2V)
±0.04mV (due to the +PSRR = 0.2mV/V ±0.2V)
Total = ±0.72mV
This would be the worst-case error band in volume produc-
tion at 25°C acceptance testing given the conditions stated.
Over the temperature range (0°C to 70°C), we can expect the
following worst-case shifting from initial value. A 20°C inter-
nal junction self-heating is assumed here.
±0.36mV (OPA656 high-grade input offset drift)
= ±6µV/°C (70°C + 20°C 25°C)
±0.11mV (PSRR of 66dB with 5mV (70°C 25°C) supply shift)
±0.04mV (+PSRR of 76dB with 5mV (70°C 25°C) supply shift)
Total = ±0.51mV
This would be the worst-case shift from an initial offset over
a 0°C to 70°C ambient for the conditions stated. Typical initial
output DC error bands and shifts over temperature will be
much lower than these worst-case estimates.
In the transimpedance configuration, the CMRR errors can
be neglected since the input common-mode voltage is held
at ground. For noninverting gain configurations (Figure 1),
the CMRR term will need to be considered but will typically
be far lower than the input offset voltage term. With a tested
minimum of 91dB (28µV/V), the added apparent DC error will
be no more than ±0.06mV for a ±2V input swing to the circuit
of Figure 1.
POWER-SUPPLY CONSIDERATIONS
The OPA657 is intended for operation on ±5V supplies.
Single-supply operation is allowed with minimal change from
the stated specifications and performance from a single
supply of +8V to +12V maximum. The limit to lower supply
voltage operation is the useable input voltage range for the
JFET-input stage. Operating from a single supply of +12V
can have numerous advantages. With the negative supply at
ground, the DC errors due to the PSRR term can be
minimized. Typically, AC performance improves slightly at
+12V operation with minimal increase in supply current.
THERMAL ANALYSIS
The OPA657 will not require heatsinking or airflow in most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
θ
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. P
DL
will depend on the
required output signal and load but wouldfor a grounded
resistive loadbe at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition P
DL
= V
S
2
/(4 R
L
)
where R
L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA657N (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 100 load.
P
D
= 10V 16.1mA + 5
2
/(4 (100 || 500)) = 236mW
Maximum T
J
= +85°C + (0.24W 150°C/W) = 121°C.
All actual applications will be operating at lower internal
power and junction temperature.
BOARD LAYOUT
Achieving optimum performance with a high-frequency am-
plifier like the OPA657 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instabilityon the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.