Datasheet

OPA656
14
SBOS196G
www.ti.com
a careful control of the negative supply voltage is required.
The +PSRR is tested to a minimum value of 74dB. This
translates into 10
(–74/20)
= 0.2mV/V sensitivity for the input
offset voltage to positive power supply changes.
As an example, compute the worst-case output DC error for
the transimpedance circuit of Figure 1 at 25°C and then the
shift over the 0°C to 70°C range given the following assump-
tions.
Negative Power Supply
= –5V ±0.2V with a ±5mV/°C worst-case shift
Positive Power Supply
= +5V ±0.2V with a ±5mV/°C worst-case shift
Initial 25°C Output DC Error Band
= ±0.3mV (due to the –PSRR = 1.59mV/V • ±0.2V)
±0.04mV (due to the +PSRR = 0.2mV/V • ±0.2V)
±0.6mV Input Offset Voltage
Total = ±0.94mV
This would be the worst-case error band in volume produc-
tion at 25°C acceptance testing given the conditions stated.
Over the temperature range of 0°C to 70°C, we can expect
the following worst-case shifting from initial value. A 20°C
internal junction self heating is assumed here.
±0.36mV (OPA656 high-grade input offset drift)
= ±6µV/°C • (70°C + 20°C – 25°C))
±0.23mV (–PSRR of 60dB with 5mV • (70°C – 25°C) supply shift)
±0.06mV (+PSRR of 72dB with 5mV • (70°C – 25°C) supply shift)
Total = ±0.65mV
This would be the worst-case shift from initial offset over a
0°C to 70°C ambient for the conditions stated. Typical initial
output DC error bands and shifts over temperature will be
much lower than these worst-case estimates.
In the transimpedance configuration, the CMRR errors can be
neglected since the input common mode voltage is held at
ground. For noninverting gain configurations (see Figure 1), the
CMRR term will need to be considered but will typically be far
lower than the input offset voltage term. With a tested minimum
of 80dB (100µV/V), the added apparent DC error will be no more
than ±0.2mV for a ±2V input swing to the circuit of Figure 1.
POWER-SUPPLY CONSIDERATIONS
The OPA656 is intended for operation on ±5V supplies.
Single-supply operation is allowed with minimal change from
the stated specifications and performance from a single
supply of +8V to +12V maximum. The limit to lower supply
voltage operation is the useable input voltage range for the
JFET-input stage. Operating from a single supply of +12V
can have numerous advantages. With the negative supply at
ground, the DC errors due to the –PSRR term can be
minimized. Typically, AC performance improves slightly at
+12V operation with minimal increase in supply current.
THERMAL ANALYSIS
The OPA656 will not require heatsinking or airflow in most
applications. Maximum allowed junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 150°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
• θ
JA
.
The total internal power dissipation (P
D
) is the sum of quiescent
power (P
DQ
) and additional power dissipated in the output stage
(P
DL
) to deliver load power. Quiescent power is simply the
specified no-load supply current times the total supply voltage
across the part. P
DL
will depend on the required output signal
and load but would, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to 1/2 of
either supply voltage (for equal bipolar supplies). Under this
condition P
DL
= V
S
2
/(4 • R
L
) where R
L
includes feedback
network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA656N (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 100Ω load.
P
D
= 10V • 16.1mA + 5
2
/(4 • (100Ω || 800Ω)) = 231mW
Maximum T
J
= +85°C + (0.23W • 150°C/W) = 120°C.
All actual applications will be operating at lower internal
power and junction temperature.
BOARD LAYOUT
Achieving optimum performance with a high-frequency am-
plifier like the OPA656 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability—on the noninvert-
ing input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25”) from the power-supply
pins to high-frequency 0.1uF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective
at lower frequency, should also be used on the supply pins.
These may be placed somewhat farther from the device and
may be shared among several devices in the same area of
the PC board.