Datasheet

External
Pin
Internal
Circuitry
-V
CC
+V
CC
OPA653
SBOS348A –DECEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
Other network components, such as noninverting well as a doubly-terminated line. If the input
input termination resistors, should also be placed impedance of the destination device is low, there will
close to the package. Even with a low parasitic be some signal attenuation as a result of the voltage
capacitance, excessively high resistor values can divider formed by the series output into the
create significant time constants that can degrade terminating impedance.
device performance. Good axial metal film or
e) Socketing a high-speed part such as the
surface-mount resistors have approximately 0.2 pF in
OPA653 is not recommended. The additional lead
shunt with the resistor. For resistor values greater
length and pin-to-pin capacitance introduced by the
than 1.5 kΩ, this parasitic capacitance can add a pole
socket can create an extremely troublesome parasitic
and/or zero below 500 MHz that can affect circuit
network that can make it almost impossible to
operation. Keep resistor values as low as possible.
achieve a smooth, stable frequency response. Best
Using values less than 500 Ω automatically holds the
results are obtained by soldering the OPA653 directly
resistor noise terms low, and minimizes the effects of
onto the board.
parasitic capacitance.
d) Connections to other wideband devices on the
Input and ESD Protection
board may be made with short direct traces or
The OPA653 is built using a very high-speed
through onboard transmission lines. For short
complementary bipolar process. The internal junction
connections, consider the trace and the input to the
breakdown voltages are relatively low for these very
next device as a lumped capacitive load. Relatively
small geometry devices. These breakdowns are
wide traces (50 mils to 100 mils, or 1,27 cm to 2,54
reflected in the Absolute Maximum Ratings table. All
cm) should be used. Estimate the total capacitive
device pins are protected with internal ESD protection
load and set R
ISO
from the plot of Recommended
diodes to the power supplies, as Figure 25 shows.
R
ISO
vs Capacitive Load (Figure 17). Low parasitic
capacitive loads (less than 5 pF) may not need an
R
ISO
because the OPA653 is nominally compensated
to operate with a 2-pF parasitic load.
Higher parasitic capacitive loads without an R
ISO
are
allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required,
and the 6-dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
Figure 25. Internal ESD Protection
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50-Ω environment is normally
These diodes provide moderate protection to input
not necessary onboard, and in fact a higher
overdrive voltages above the supplies as well. The
impedance environment improves distortion as shown
protection diodes can typically support 30-mA
in the distortion versus load plots. With a
continuous current. Where higher currents are
characteristic board trace impedance defined based
possible (for example, in systems with ±12-V supply
on board material and trace dimensions, a matching
parts driving into the OPA653), current limiting series
series resistor into the trace from the output of the
resistors should be added into the two inputs. Keep
OPA653 is used as well as a terminating shunt
these resistor values as low as possible because high
resistor at the input of the destination device.
values degrade both noise performance and
Remember also that the terminating impedance is the
frequency response.
parallel combination of the shunt resistor and the
input impedance of the destination device: this total
PowerPAD™ Information
effective impedance should be set to match the trace
The DRB package option is a PowerPAD™ package
impedance. If the 6-dB attenuation of a
that includes a thermal pad for increased thermal
doubly-terminated transmission line is unacceptable,
performance. When using thls package, it is
a long trace can be series-terminated at the source
recommended to distribute the negative supply as a
end only. Treat the trace as a capacitive load in this
power plane, and tie the PowerPAD to this supply
case, and set the series resistor value as shown in
wlth multiple vias for proper power dissipation.
the plot of R
ISO
vs Capacitive Load (Figure 17). This
configuration does not preserve signal integrity as
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