Datasheet

OPA653
www.ti.com SBOS348A –DECEMBER 2008–REVISED NOVEMBER 2009
The Typical Characteristics show the recommended Board Layout
R
ISO
versus Capacitive Load performance (see
Achieving optimum performance with a
Figure 17) and the resulting frequency response with
high-frequency amplifier such as the OPA653
a 1-kΩ load. Note that larger R
ISO
values are required
requires careful attention to PCB layout parasitics and
for lower capacitive loading. In this case, a design
external component types. Recommendations that
target of a maximally-flat frequency response was
can optimize device performance include the
used. Lower values of R
ISO
may be used if some
following.
peaking can be tolerated. Long PCB traces,
unmatched cables, and connections to multiple
a) Minimize parasitic capacitance to any ac ground
devices can easily degrade the performance of the
for all of the signal input/output (I/O) pins. Parasitic
OPA653. Always consider this effect carefully, and
capacitance on the output and inverting input pins
add the recommended series resistor as close as
can cause instability: on the noninverting input, it can
possible to the OPA653 output pin (see the Board
react with the source impedance to cause
Layout section). With heavier loads (for example, the
unintentional band-limiting. To reduce unwanted
100-Ω load presented in the test circuits used for
capacitance, a window around the signal I/O pins
testing the Typical Characteristics), the OPA653 is
should be opened in all of the ground and power
very robust; R
ISO
can be as low as 10 Ω with
planes around those pins. Otherwise, ground and
capacitive loads less than 5 pF and continue to show
power planes should be unbroken elsewhere on the
a flat frequency response.
board.
b) Minimize the distance (less than 0.25 in, or 6,35
Distortion Performance
mm) from the power-supply pins to the
The OPA653 is capable of delivering low distortion at high-frequency, 0.1-μF decoupling capacitors. At the
high frequencies. The distortion plots in the Typical device pins, the ground and power plane layout
Characteristics show the typical distortion under a should not be in close proximity to the signal I/O pins.
wide variety of conditions. Generally, the best Use a single point ground, located away from the
distortion performance can be achieved using higher input pins, for the positive and negative supply
power-supply voltage (±6 V is recommended), lower high-frequency, 0.1-μF decoupling capacitors. Avoid
output voltage swings, and lower loads. narrow power and ground traces to minimize
inductance between the pins and the decoupling
The total load includes the feedback network—in the
capacitors. The power-supply connections should
noninverting configuration, this value is the sum of
always be decoupled with these capacitors. Larger
R
F
+ R
G
= 320 Ω, while in the inverting configuration
(2.2-μF to 10-μF) decoupling capacitors, effective at
the total load is only R
F
= 160 Ω (see Figure 22).
lower frequencies, should also be used on the supply
pins. These larger capacitors may be placed
Power-supply decoupling is critical for harmonic
somewhat farther from the device and may be shared
distortion performance. In particular, for optimal
among several devices in the same area of the PCB.
second-harmonic performance, the high-frequency,
0.1-μF, power-supply decoupling capacitors should
c) Careful selection and placement of external
be as close as posible to the positive and negative
components preserves the high-frequency
supply pins and should be brought to a single point
performance of the OPA653. Resistors should be a
ground away from the input pins.
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal film
Pulse and Transient Response
and carbon composition, axially-leaded resistors can
also provide good high-frequency performance.
To achieve optimum pulse and transient response,
Again, keep the leads and PCB trace length as short
the OPA653 should be used in a noise gain of +2 V/V
as possible. Never use wirewound-type resistors in a
configuration, with minimal capacitance at the output,
high-frequency application. The inverting input pin is
and high-frequency, 0.1-μF, power-supply decoupling
the most sensitive to parasitic capacitance;
capacitors as close the power pins as possible.
consequently, always position the feedback resistor
Note: Noise gain of +2 V/V is achieved by tying V
IN–
as close to the negative input as possible. The output
to a 0-Ω point. In noninverting gain of +2 V/V
is also sensitive to parasitic capacitance; therefore,
applications, V
IN–
should be grounded, and in
position a series output resistor (in this case, R
ISO
) as
inverting gain of –1 V/V applications, V
IN–
should be
close to the output pin as possible.
driven from a near-0-Ω source such as an op amp.
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