Datasheet

External
Pin
+V
CC
−
V
CC
Internal
Circuitry
OPA615
www.ti.com ...................................................................................................................................... SBOS299E –FEBRUARY 2004–REVISED SEPTEMBER 2009
BOARD LAYOUT GUIDELINES d) Connections to other wideband devices on the
board may be made with short direct traces or
Achieving optimum performance with a high-
through onboard transmission lines. For short
frequency amplifier such as the OPA615 requires
connections, consider the trace and the input to the
careful attention to printed circuit board (PCB) layout
next device as a lumped capacitive load. Relatively
parasitics and external component types.
wide traces (50mils to 100mils) should be used,
Recommendations that will optimize performance
preferably with ground and power planes opened up
include:
around them.
a) Minimize parasitic capacitance to any AC
e) Socketing a high-speed part such as the
ground for all of the signal I/O pins. Parasitic
OPA615 is not recommended. The additional lead
capacitance on the output and inverting input pins
length and pin-to-pin capacitance introduced by the
can cause instability; on the non-inverting input, it can
socket can create an extremely troublesome parasitic
react with the source impedance to cause
network which can make it almost impossible to
unintentional bandlimiting. To reduce unwanted
achieve a smooth, stable frequency response. Best
capacitance, a window around the signal I/O pins
results are obtained by soldering the OPA615 directly
should be opened in all of the ground and power
onto the PCB.
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
INPUT AND ESD PROTECTION
board.
The OPA615 is built using a very high-speed,
b) Minimize the distance (< 0.25") from the power
complementary bipolar process. The internal junction
supply pins to high frequency 0.1μF decoupling
breakdown voltages are relatively low for these very
capacitors. At the device pins, the ground and power
small geometry devices. These breakdowns are
plane layout should not be in close proximity to the
reflected in the Absolute Maximum Ratings table
signal I/O pins. Avoid narrow power and ground
where an absolute maximum ±6.5V supply is
traces to minimize inductance between the pins and
reported. All device pins have limited ESD protection
the decoupling capacitors. The power-supply
using internal diodes to the power supplies, as shown
connections should always be decoupled with these
in Figure 53.
capacitors. An optional supply-decoupling capacitor
across the two power supplies (for bipolar operation)
will improve 2nd-harmonic distortion performance.
Larger (2.2μF to 6.8μF) decoupling capacitors,
effective at a lower frequency, should also be used
on the main supply pins. These may be placed
somewhat farther from the device and may be shared
among several devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high frequency
performance of the OPA615. Resistors should be a
very low reactance type. Surface-mount resistors
Figure 53. Internal ESD Protection
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
These diodes also provide moderate protection to
also provide good high frequency performance.
input overdrive voltages above the supplies. The
Again, keep these leads and PCB trace length as
protection diodes can typically support 30mA
short as possible. Never use wirewound-type
continuous current. Where higher currents are
resistors in a high frequency application. Other
possible (for example, in systems with ±15V supply
network components, such as noninverting input
parts driving into the OPA615), current-limiting series
termination resistors, should also be placed close to
resistors should be added into the two inputs. Keep
the package.
these resistor values as low as possible since high
values degrade both noise performance and
frequency response.
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Product Folder Link(s): OPA615