Datasheet

V =V (R I ) G´
OSO_envelope OS S b
´ ´G I xR
bi F
± ±
±½- - ½ ´5 (V ) 10
S-
-
PSRR-
20
± ½ -5 (V ) 10
S+
½ ´
-
PSRR+
20
±½- - - ½ ´5 ( 6) 10
-
51
20
50
20
±½ - ½ ´5 6 10
-
= 29.2mV±
+523 18 AW ´ ± m
± ´ ± ´10mV+75 14 A 2W m
OPA4872
www.ti.com SBOS346C –JUNE 2007–REVISED MARCH 2011
DRIVING CAPACITIVE LOADS
One of the most demanding, yet very common load
conditions, is capacitive loading. Often, the capacitive
load is the input of an analog-to-digital converter
(7)
(ADC)—including additional external capacitance that
Where:
may be recommended to improve ADC linearity. A
R
S
: Input resistance seen by R0, R1, G0, G1, B0,
high-speed device such as the OPA4872 can be very
or B1.
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
I
b
: Noninverting input bias current
directly on the output pin. When the device open-loop
I
bi
: Inverting input bias current
output resistance is considered, this capacitive load
G: Gain
introduces an additional pole in the signal path that
V
S+
: Positive supply voltage
can decrease the phase margin. Several external
solutions to this problem have been suggested. When
V
S–
: Negative supply voltage
the primary considerations are frequency response
PSRR+: Positive supply PSRR
flatness, pulse response fidelity, and/or distortion, the
PSRR–: Negative supply PSRR
simplest and most effective solution is to isolate the
V
OS
: Input Offset Voltage
capacitive load from the feedback loop by inserting a
series isolation resistor between the amplifier output
Evaluating the front-page schematic, using a
and the capacitive load. This isolation resistor does
worst-case, +25°C offset voltage, bias current and
not eliminate the pole from the loop response, but
PSRR specifications and operating at ±6V, gives a
rather shifts it and adds a zero at a higher frequency.
worst-case output equal to Equation 8:
The additional zero acts to cancel the phase lag from
the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Characteristics show the recommended
R
S
versus capacitive load and the resulting frequency
(8)
response at the load; see Figure 5. Parasitic
capacitive loads greater than 2pF can begin to
DISTORTION PERFORMANCE
degrade the performance of the OPA4872. Long PCB
The OPA4872 provides good distortion performance
traces, unmatched cables, and connections to
into a 150Ω load on ±5V supplies. Relative to
multiple devices can easily cause this value to be
alternative solutions, it provides exceptional
exceeded. Always consider this effect carefully, and
performance into lighter loads. Generally, until the
add the recommended series resistor as close as
fundamental signal reaches very high frequency or
possible to the OPA4872 output pin (see the Board
power levels, the 2nd harmonic dominates the
Layout Guidelines section).
distortion with a negligible 3rd harmonic component.
Focusing then on the 2nd harmonic, increasing the
DC ACCURACY
load impedance directly improves distortion. Also,
The OPA4872 offers excellent dc signal accuracy.
providing an additional supply decoupling capacitor
Parameters that influence the output dc offset voltage
(0.01μF) between the supply pins (for bipolar
are:
operation) improves the 2nd-order distortion slightly
• Output offset voltage
(3dB to 6dB).
• Input bias current
In most op amps, increasing the output voltage swing
• Gain error
increases harmonic distortion directly. The Typical
• Power-supply rejection ratio
Characteristics show the 2nd harmonic increasing at
a little less than the expected 2X rate while the 3rd
• Temperature
harmonic increases at a little less than the expected
3X rate. Where the test power doubles, the 2nd
Leaving both temperature and gain error parameters
harmonic increases only by less than the expected
aside, the output offset voltage envelope can be
6dB, whereas the 3rd harmonic increases by less
described as shown in Equation 7:
than the expected 12dB.
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