Datasheet

BOARD LAYOUT GUIDELINES
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 .................................................................................................................................................... www.ti.com
shunt with the resistor. For resistor values > 1.5k Ω ,
this parasitic capacitance can add a pole and/or zero
Achieving optimum performance with a
below 500MHz that can effect circuit operation. Keep
high-frequency amplifier like the OPA4830 requires
resistor values as low as possible consistent with
careful attention to board layout parasitics and
load driving considerations. The 750 Ω feedback used
external component types. Recommendations that
in the Typical Characteristics is a good starting point
optimize performance include:
for design.
a) Minimize parasitic capacitance to any ac ground
d) Connections to other wideband devices on the
for all of the signal I/O pins. Parasitic capacitance on
board may be made with short direct traces or
the output and inverting input pins can cause
through onboard transmission lines. For short
instability: on the noninverting input, it can react with
connections, consider the trace and the input to the
the source impedance to cause unintentional
next device as a lumped capacitive load. Relatively
bandlimiting. To reduce unwanted capacitance, a
wide traces (50mils to 100mils) should be used,
window around the signal I/O pins should be opened
preferably with ground and power planes opened up
in all of the ground and power planes around those
around them. Estimate the total capacitive load and
pins. Otherwise, ground and power planes should be
set R
S
from the typical characteristic curve
unbroken elsewhere on the board.
Recommended R
S
vs Capacitive Load (Figure 15 ,
Figure 38 , or Figure 63 ). Low parasitic capacitive
b) Minimize the distance ( < 0.25 ” ) from the
loads (< 5pF) may not need an R
S
because the
power-supply pins to high-frequency 0.1 µ F
OPA4830 is nominally compensated to operate with a
decoupling capacitors. At the device pins, the ground
2pF parasitic load. Higher parasitic capacitive loads
and power-plane layout should not be in close
without an R
S
are allowed as the signal gain
proximity to the signal I/O pins. Avoid narrow power
increases (increasing the unloaded phase margin). If
and ground traces to minimize inductance between
a long trace is required, and the 6dB signal loss
the pins and the decoupling capacitors. Each
intrinsic to a doubly-terminated transmission line is
power-supply connection should always be
acceptable, implement a matched impedance
decoupled with one of these capacitors. An optional
transmission line using microstrip or stripline
supply decoupling capacitor (0.1 µ F) across the two
techniques (consult an ECL design handbook for
power supplies (for bipolar operation) improves
microstrip and stripline layout techniques). A 50 Ω
2nd-harmonic distortion performance. Larger (2.2 µ F
environment is normally not necessary onboard, and
to 6.8 µ F) decoupling capacitors, effective at lower
in fact, a higher impedance environment improves
frequency, should also be used on the main supply
distortion as shown in the distortion versus load plots.
pins. These may be placed somewhat farther from
With a characteristic board trace impedance defined
the device and may be shared among several
(based on board material and trace dimensions), a
devices in the same area of the PCB.
matching series resistor into the trace from the output
c) Careful selection and placement of external
of the OPA4830 is used as well as a terminating
components preserve the high-frequency
shunt resistor at the input of the destination device.
performance. Resistors should be a very low
Remember also that the terminating impedance is the
reactance type. Surface-mount resistors work best
parallel combination of the shunt resistor and the
and allow a tighter overall layout. Metal film or carbon
input impedance of the destination device; this total
composition axially-leaded resistors can also provide
effective impedance should be set to match the trace
good high-frequency performance. Again, keep the
impedance. If the 6dB attenuation of a
leads and PCB traces as short as possible. Never
doubly-terminated transmission line is unacceptable,
use wire-wound type resistors in a high-frequency
a long trace can be series-terminated at the source
application. Because the output pin and inverting
end only. Treat the trace as a capacitive load in this
input pin are the most sensitive to parasitic
case and set the series resistor value as shown in the
capacitance, always position the feedback and series
typical characteristic curve Recommended R
S
vs
output resistor, if any, as close as possible to the
Capacitive Load (Figure 15 , Figure 38 , or Figure 63 ).
output pin. Other network components, such as
This configuration does not preserve signal integrity
noninverting input termination resistors, should also
as well as a doubly-terminated line. If the input
be placed close to the package. Where double-side
impedance of the destination device is low, there will
component mounting is allowed, place the feedback
be some signal attenuation due to the voltage divider
resistor directly under the package on the other side
formed by the series output into the terminating
of the board between the output and inverting input
impedance.
pins. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor values
can create significant time constants that can
degrade performance. Good axial metal film or
surface-mount resistors have approximately 0.2pF in
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