Datasheet

OPEN-LOOP GAIN LINEARITY SETTLING TIME
-50 0-40 -30 -20 -10 10 30 40 50
OutputVoltage(V)
|(V
)
(V-
)|
IN+ IN-
20
A isaFunctionofV andI
OL OUT LOAD
T =+25 C
P
°
R
L
=1880W,1mV/div
89dB
106dB
74dB
R
L
=900W,2mV/div
R =4.87kW m
L
,200 V/div
R
7
R
8
R
10kW
5
R
10kW
6
R
3
R
10kW
4
R
1
R
10kW
2
InvertingResponse
MeasuredHere,V
1
CombinationofBoth
Invertingand
NoninvertingResponses,V
2
V
IN
-IN
+IN
V
OUT
OPA454 OPA454
V
OUT
-IN
+IN
A
1
A
2
OPA454
www.ti.com ....................................................................................................................................... SBOS391A – DECEMBER 2007 – REVISED DECEMBER 2008
Figure 65 shows the nonlinear relationship of A
OL
and The circuit in Figure 66 is used to measure the
output voltage. As Figure 65 shows, open-loop gain is settling time response. The left half of the circuit is a
lower with positive output voltage levels compared to standard, false-summing junction test circuit used for
negative voltage levels. Specifications in the settling time and open-loop gain measurement. R
1
Electrical Characteristics table are based upon the and R
2
provide the gain and allow for measurement
average gain measured at both output extremes. without connecting a scope probe directly to the
summing junction, which can disturb proper op amp
function by causing oscillation.
The right half of the circuit looks at the combination of
both inverting and noninverting responses. R
5
and R
6
remove the large step response. The remaining
voltage at V
2
shows the small-signal settling time that
is centered on zero. This test circuit can be used for
incoming inspection, real-time measurement, or in
designing compensation circuits in system
applications.
Table 2. Settling Time Measurement Circuit
Configuration Using Different Gain Settings for
Figure 66
GAIN
COMPONENT 1 5 10
Figure 65. Differential Input Voltage (+IN to – IN)
R
1
( Ω ) 10k 2k 1k
versus Output Voltage
R
3
( Ω ) 10k 2k 1k
R
7
( Ω ) 10k 4k 9k
R
8
( Ω ) ∞ 1k 1k
V
IN
(V
PP
) 20 16 8
Figure 66. Settling Time Test Measurement Circuit
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): OPA454