Datasheet

BOARD LAYOUT GUIDELINES
THERMAL ANALYSIS
P
D
10V 12.75mA
3 5
2
4
150W 800W
276mV
Maximum T
J
85°C 0.276W 100°C W 113°C
OPA3832
www.ti.com ............................................................................................................................................ SBOS370A – DECEMBER 2006 – REVISED AUGUST 2008
A fine-scale output offset null, or dc operating point dissipation will occur if the load requires current to be
adjustment, is often required. Numerous techniques forced into the output at high output voltages or
are available for introducing dc offset control into an sourced from the output at low output voltages. This
op amp circuit. Most of these techniques are based condition puts a high current through a large internal
on adding a dc current through the feedback resistor. voltage drop in the output transistors.
In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
Achieving optimum performance with a
be noninverting, the offset control is best applied as
high-frequency amplifier such as the OPA3832
an inverting summing signal to avoid interaction with
requires careful attention to board layout parasitics
the signal source. If the signal path is intended to be
and external component types. Recommendations
inverting, applying the offset control to the
that will optimize performance include:
noninverting input may be considered. Bring the dc
offsetting current into the inverting input node through
a) Minimize parasitic capacitance to any ac ground
resistor values that are much larger than the signal
for all of the signal I/O pins. Parasitic capacitance on
path resistors. This configuration ensures that the
the output and inverting input pins can cause
adjustment circuit has minimal effect on the loop gain
instability; on the noninverting input, it can react with
and thus the frequency response.
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
Maximum desired junction temperature sets the
pins. Otherwise, ground and power planes should be
maximum allowed internal power dissipation, as
unbroken elsewhere on the board.
described below. In no case should the maximum
junction temperature be allowed to exceed +150 ° C.
b) Minimize the distance ( < 0.25") from the
power-supply pins to high-frequency 0.1 µ F
Operating junction temperature (T
J
) is given by
decoupling capacitors. At the device pins, the ground
T
A
+ P
D
× θ
JA
. The total internal power dissipation
and power-plane layout should not be in close
(P
D
) is the sum of quiescent power (P
DQ
) and
proximity to the signal I/O pins. Avoid narrow power
additional power dissipated in the output stage (P
DL
)
and ground traces to minimize inductance between
to deliver load power. Quiescent power is simply the
the pins and the decoupling capacitors. Each
specified no-load supply current times the total supply
power-supply connection should always be
voltage across the part. P
DL
depends on the required
decoupled with one of these capacitors. An optional
output signal and load, though for resistive loads
supply decoupling capacitor (0.1 µ F) across the two
connected to midsupply (V
S
/2), P
DL
is at a maximum
power supplies (for bipolar operation) will improve
when the output is fixed at a voltage equal to V
S
/4 or
2nd-harmonic distortion performance. Larger (2.2 µ F
3V
S
/4. Under this condition, P
DL
= V
S
2
/(4 × R
L
), where
to 6.8 µ F) decoupling capacitors, effective at lower
R
L
includes feedback network loading.
frequency, should also be used on the main supply
Note that it is the power in the output stage, and not pins. These may be placed somewhat farther from
into the load, that determines internal power the device and may be shared among several
dissipation. devices in the same area of the PCB.
As a worst-case example, compute the maximum T
J
c) Careful selection and placement of external
using an OPA3832 (TSSOP-14 package) in the circuit components will preserve the high-frequency
of Figure 48 operating at the maximum specified performance. Resistors should be a very low
ambient temperature of +85 ° C and driving both reactance type. Surface-mount resistors work best
channels at a 150 Ω load at mid-supply. and allow a tighter overall layout. Metal film or carbon
composition axially-leaded resistors can also provide
good high-frequency performance. Again, keep the
leads and PCB traces as short as possible. Never
use wire-wound type resistors in a high-frequency
application. Since the output pin and inverting input
Although this value is still well below the specified
pin are the most sensitive to parasitic capacitance,
maximum junction temperature, system reliability
always position the series output resistor, if any, as
considerations may require lower ensured junction
close as possible to the output pin. Other network
temperatures. The highest possible internal
components, such as noninverting input termination
resistors, should also be placed close to the package.
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