Datasheet

−
5V
V
−
Optional
(2)
C
1
100nF
R
1
(1)
100
Ω
R
2
500
Ω
C
2
100nF
V+
+5V
SD1
BAS40
V
IN
0 to 4.096V
ADS8326
16Bit
250kSPS
C
3
(1)
1nF
C
4
100nF
+5V
REF IN
−
IN
+IN
REF3240
4.096V
+5V
OPA365
V
−
C
1
100nF
R
2
10k
Ω
R
1
10k
Ω
R
3
(A)
100
Ω
R
4
20k
Ω
R
5
480k
Ω
V+
+5V
V
IN
0.1V to 4.9V
ADS8361
16Bit
100kSPS
OPA365
C
2
(A)
1nF
C
1
3
µ
F
REF IN
+IN
−
IN
+5V
REF OUT
+2.5V
+2.4V
OPA365-EP
SLOS735 –AUGUST 2011 www.ti.com
Figure 11. Driving the ADS8326
One method for driving an ADC that negates the need for an output swing down to 0 V uses a slightly
compressed ADC full-scale input range (FSR). For example, the 16-bit ADS8361 (shown in Figure 12) has a
maximum FSR of 0 V to 5 V, when powered by a 5-V supply and V
REF
of 2.5 V. The idea is to match the ADC
input range with the op amp full linear output swing range; for example, an output range of 0.1 V to 4.9 V. The
reference output from the ADS8361 ADC is divided down from 2.5 V to 2.4 V using a resistive divider. The ADC
FSR then becomes 4.8V
PP
centered on a common-mode voltage of 2.5 V. Current from the ADS8361 reference
pin is limited to about ±10 µA. Here, 5 µA was used to bias the divider. The resistors must be precise to maintain
the ADC gain accuracy. An additional benefit of this method is the elimination of the negative supply voltage; it
requires no additional power-supply current.
Figure 12. Driving the ADS8361
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