Datasheet

1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
A
B
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
Exposed
Thermal
DiePad
on
Underside
(2)
1
2
3
4
5
6
7
V+
+INB
-INB
OUTB
+INA
-INA
OUTA
+INC
-INC
OUTC
+IND
-IND
OUTD
V-
14
13
12
11
10
9
8
DA
B C
14
1
8
7
-INA
+INA
V+
+INB
-INB
-IND
+IND
V-
+INC
-INC
OUTA
OUTB
OUTD
OUTC
Exposed
ThermalDie
Padon
Underside
(2)
2
3
5
6
4
13
12
10
9
11
1
2
3
4
5
6
7 8
14
13
12
11
10
9
V+
+INB
-INB
OUTB
+INA
-INA
OUTA
+INC
-INC
OUTC
+IND
-IND
OUTD
V-
OPA330
OPA2330
OPA4330
SBOS432E –AUGUST 2008– REVISED FEBRUARY 2011 www.ti.com
PIN CONFIGURATIONS, CONTINUED
OPA2330
OPA2330
SOIC-8, MSOP-8
DFN-8
(TOP VIEW)
(TOP VIEW)
OPA4330
OPA4330
SOIC-14
QFN-14
(TOP VIEW)
(TOP VIEW)
OPA4330
TSSOP-14
(TOP VIEW)
(2) Connect thermal die pad to V–.
6 Submit Documentation Feedback © 2008–2011, Texas Instruments Incorporated
Product Folder Link(s): OPA330 OPA2330 OPA4330