Datasheet

t =2RC
GR0
t =2(2RC+T )
GR D
R
R
F
402W
R
G
402W
R
F
402W
R
G
402W
V
IN
V
OUT
R
1/2
OPA2890
OPA890
C
C
1/2
OPA2890
750W
750W
OPA2890
www.ti.com SBOS364C –DECEMBER 2007–REVISED DECEMBER 2009
Typically, channel switching is performed either on
sync or retrace time in the video signal. The two
HIGH-SPEED DELAY CIRCUIT
inputs are approximately equal at this point. The
The OPA2890 makes an ideal amplifier for a variety
make-before-break disable characteristic of the
of active filter designs. Figure 55 illustrates a circuit
OPA2890 ensures that there is always one amplifier
that uses the two amplifiers within the dual OPA2890
controlling the line when using a wired-OR circuit
to design a two-stage analog delay circuit. For
such as that shown in Figure 54. Because both inputs
simplicity, the circuit uses a dual-supply (±5V)
may be on for a short period during the transition
operation, but it can also be modified to operate on a
between channels, the outputs are combined through
signal supply. The input to the first filter stage is
the output impedance matching resistors (82.5Ω in
driven by the OPA890 as a gain of +2V/V to isolate
this case). When one channel is disabled, its
the signal input from the filter network.
feedback network forms part of the output impedance
and slightly attenuates the signal in getting out onto
Each of the two filter stages is a 1st-order filter with a
the cable. The gain and output matching resistor are
voltage gain of +1V/V. The delay time through one
slightly increased to get a signal gain of +1V/V at the
filter is given by Equation 3.
matched load and provide a 75Ω output impedance
(3)
to the cable. The video multiplexer connection (see
Figure 54) also ensures that the maximum differential
For a more accurate analysis of the circuit, consider
voltage across the inputs of the unselected channel
the group delay for the amplifiers. For example, in the
does not exceed the rated ±1.2V maximum for
case of the OPA2890, the group delay in the
standard video signal levels.
bandwidth from 1MHz to 100MHz is approximately
1.0ns. To account for this delay, modify the transfer
See the Disable Operation section for the turn-on and
function, which now comes out to be:
turn-off switching glitches using a 0V input for a
single channel is typically less than ±50mV. Where
(4)
two outputs are switched (see Figure 54), the output
with T
D
= (1/360) × (dφ/df) = delay of the op amp
line is always under the control of one amplifier or the
itself. The values of resistors R
F
and R
G
should be
other as a result of the make-before-break disable
equal and low to avoid parasitic effects. If the all-pass
timing. In this case, the switching glitches for two 0V
filter is designed for very low delay times, include
inputs drops to less than 20mV.
parasitic board capacitances to calculate the correct
delay time. Simulating this application using the
PSpice model of the OPA2890 allows this design to
be tuned to the desired performance.
Figure 55. Two-Stage, All-Pass Network
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