Datasheet

P =10V 2.5mA+2[5 /(4 (75 ||1.5k ))]=200mW´ ´ W W
D
2
MaximumT =+85 C+(200mW 125 C/W)=+110 C° ´ ° °
J
BOARD LAYOUT GUIDELINES
OPA2889
www.ti.com ....................................................................................................................................................... SBOS373B – JUNE 2007 – REVISED AUGUST 2008
As a worst-case example, compute the maximum T
J
Again, keep the leads and PCB traces as short as
using an OPA2889ID (SO-8 package) in the circuit of possible. Never use wirewound type resistors in a
Figure 50 operating at the maximum specified high-frequency application. Since the output pin and
ambient temperature of +85 ° C and with both outputs inverting input pin are the most sensitive to parasitic
driving a grounded 75 Ω load to +2.5V. capacitance, always position the feedback and series
output resistor, if any, as close as possible to the
output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Even with a low
parasitic capacitance shunting the external resistors,
excessively high resistor values can create significant
This absolute worst-case condition does not exceed
time constants that can degrade performance. Good
the specified maximum junction temperature. Actual
axial metal film or surface-mount resistors have
P
DL
is normally less than that considered here.
approximately 0.2pF in shunt with the resistor. For
Carefully consider maximum T
J
in your application.
resistor values > 1.5k Ω , this parasitic capacitance
can add a pole and/or zero below 500MHz that can
effect circuit operation. Keep resistor values as low
as possible consistent with load driving
Achieving optimum performance with a
considerations. The 750 Ω feedback used in the
high-frequency amplifier like the OPA2889 requires
Electrical Characteristics is a good starting point for
careful attention to board layout parasitics and
design. Note that a 0 Ω feedback resistor is suggested
external component types. Recommendations that
for the unity-gain follower application.
optimize performance include:
d) Connections to other wideband devices on the
a) Minimize parasitic capacitance to any ac ground
board may be made with short, direct traces or
for all of the signal I/O pins. Parasitic capacitance on
through onboard transmission lines. For short
the output and inverting input pins can cause
connections, consider the trace and the input to the
instability: on the noninverting input, it can react with
next device as a lumped capacitive load. Relatively
the source impedance to cause unintentional
wide traces (50mils to 100mils) should be used,
bandlimiting. To reduce unwanted capacitance, a
preferably with ground and power planes opened up
window around the signal I/O pins should be opened
around them. Estimate the total capacitive load and
in all of the ground and power planes around those
set R
S
from the plots of Figure 15 and Figure 16 . Low
pins. Otherwise, ground and power planes should be
parasitic capacitive loads ( < 3pF) may not need an
unbroken elsewhere on the board.
R
S
because the OPA2889 is nominally compensated
b) Minimize the distance ( < 0.25") from the
to operate with a 2pF parasitic load. Higher parasitic
power-supply pins to high-frequency 0.1 µ F
capacitive loads without an R
S
are allowed as the
decoupling capacitors. At the device pins, the ground
signal gain increases (increasing the unloaded phase
and power-plane layout should not be in close
margin; see Figure 24 ). If a long trace is required,
proximity to the signal I/O pins. Avoid narrow power
and the 6dB signal loss intrinsic to a
and ground traces to minimize inductance between
doubly-terminated transmission line is acceptable,
the pins and the decoupling capacitors. The
implement a matched impedance transmission line
power-supply connections should always be
using microstrip or stripline techniques (consult an
decoupled with these capacitors. An optional supply
ECL design handbook for microstrip and stripline
decoupling capacitor (0.1 µ F) across the two power
layout techniques). A 50 Ω environment is normally
supplies (for bipolar operation) improves
not necessary on board, and in fact, a higher
2nd-harmonic distortion performance. Larger (2.2 µ F
impedance environment improves distortion as shown
to 6.8 µ F) decoupling capacitors, effective at lower
in the distortion versus load plots. With a
frequencies, should also be used on the main supply
characteristic board trace impedance defined (based
pins. These capacitors may be placed somewhat
on board material and trace dimensions), a matching
farther from the device and may be shared among
series resistor into the trace from the output of the
several devices in the same area of the printed circuit
OPA2889 is used as well as a terminating shunt
board (PCB).
resistor at the input of the destination device.
Remember also that the terminating impedance is the
c) Careful selection and placement of external
parallel combination of the shunt resistor and the
components preserves the high-frequency
input impedance of the destination device; this total
performance of the OPA2889. Resistors should be
effective impedance should be set to match the trace
a very low reactance type. Surface-mount resistors
impedance.
work best and allow a tighter overall layout. Metal film
or carbon composition axially-leaded resistors can
also provide good high-frequency performance.
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