Datasheet

HIGH-SPEED DELAY CIRCUIT
t =2RC
GR0
(3)
t =2(2RC+T )
GR D
(4)
R
R
F
402W
R
G
402W
R
F
402W
R
G
402W
V
IN
V
OUT
R
OPA890
C
C
750W
750W
1/2
OPA2889
1/2
OPA2889
OPA2889
www.ti.com ....................................................................................................................................................... SBOS373B – JUNE 2007 – REVISED AUGUST 2008
Typically, channel switching is performed either on
sync or retrace time in the video signal. The two
The OPA2889 makes an ideal amplifier for a variety
inputs are approximately equal at this point. The
of active filter designs. Figure 56 illustrates a circuit
make-before-break disable characteristic of the
that uses the two amplifiers within the dual OPA2889
OPA2889 ensures that there is always one amplifier
to design a 2-stage analog delay circuit. For
controlling the line when using a wired-OR circuit like
simplicity, the circuit uses a dual-supply ( ± 5V)
that shown in Figure 55 . Because both inputs may be
operation, but it can also be modified to operate on a
on for a short period during the transition between
signal supply. The input to the first filter stage is
channels, the outputs are combined through the
driven by the OPA890 as a gain of +2V/V to isolate
output impedance matching resistors (82.5 Ω in this
the signal input from the filter network.
case). When one channel is disabled, its feedback
network forms part of the output impedance and
Each of the two filter stages is a 1st-order filter with a
slightly attenuates the signal in getting out onto the
voltage gain of +1V/V. The delay time through one
cable. The gain and output matching resistor are
filter is given by Equation 3 .
slightly increased to get a signal gain of +1V/V at the
matched load and provide a 75 Ω output impedance
to the cable. The video multiplexer connection (see
For a more accurate analysis of the circuit, consider
Figure 55 ) also ensures that the maximum differential
the group delay for the amplifiers. For example, in the
voltage across the inputs of the unselected channel
case of the OPA2889, the group delay in the
does not exceed the rated ± 1.2V maximum for
bandwidth from 1MHz to 100MHz is approximately
standard video signal levels.
1.0ns. To account for this delay, modify the transfer
function, which now comes out to be:
See the Disable Operation section for the turn-on and
turn-off switching glitches using a 0V input for a
single channel is typically less than ± 50mV. Where
with T
D
= (1/360) × (d φ /df) = delay of the op amp
two outputs are switched (see Figure 55 ), the output
itself. The values of resistors R
F
and R
G
should be
line is always under the control of one amplifier or the
equal and low to avoid parasitic effects. If the all-pass
other as a result of the make-before-break disable
filter is designed for very low delay times, include
timing. In this case, the switching glitches for two 0V
parasitic board capacitances to calculate the correct
inputs drops to < 20mV.
delay time. Simulating this application using the
PSPICE model of the OPA2889 allows this design to
be tuned to the desired performance.
Figure 56. 2-Stage, All-Pass Network
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Product Folder Link(s): OPA2889