Datasheet

BOARD LAYOUT GUIDELINES
THERMAL ANALYSIS
P
D
+ 10V 11.9mA )
2 5
2
ǒ
16
ǒ
150W ø 800W
Ǔ
Ǔ
+ 144mV
Maximum T
J
+ ) 85
o
C )
ǒ
0.144W 150
o
CńW
Ǔ
+ 107
o
C
OPA2832
SBOS327C – FEBRUARY 2005 – REVISED AUGUST 2008 ............................................................................................................................................. www.ti.com
A fine-scale output offset null, or DC operating point dissipation will occur if the load requires current to be
adjustment, is often required. Numerous techniques forced into the output at high output voltages or
are available for introducing DC offset control into an sourced from the output at low output voltages. This
op amp circuit. Most of these techniques are based puts a high current through a large internal voltage
on adding a DC current through the feedback drop in the output transistors.
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
Achieving optimum performance with a
be noninverting, the offset control is best applied as
high-frequency amplifier like the OPA2832 requires
an inverting summing signal to avoid interaction with
careful attention to board layout parasitics and
the signal source. If the signal path is intended to be
external component types. Recommendations that
inverting, applying the offset control to the
will optimize performance include:
noninverting input may be considered. Bring the DC
offsetting current into the inverting input node through
a) Minimize parasitic capacitance to any AC ground
resistor values that are much larger than the signal
for all of the signal I/O pins. Parasitic capacitance on
path resistors. This will insure that the adjustment
the output and inverting input pins can cause
circuit has minimal effect on the loop gain and hence
instability: on the noninverting input, it can react with
the frequency response.
the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
in all of the ground and power planes around those
Maximum desired junction temperature will set the
pins. Otherwise, ground and power planes should be
maximum allowed internal power dissipation, as
unbroken elsewhere on the board.
described below. In no case should the maximum
junction temperature be allowed to exceed +150 ° C.
b) Minimize the distance ( < 0.25") from the
power-supply pins to high-frequency 0.1 µ F
Operating junction temperature (T
J
) is given by
decoupling capacitors. At the device pins, the ground
T
A
+ P
D
× θ
JA
. The total internal power dissipation
and power-plane layout should not be in close
(P
D
) is the sum of quiescent power (P
DQ
) and
proximity to the signal I/O pins. Avoid narrow power
additional power dissipated in the output stage (P
DL
)
and ground traces to minimize inductance between
to deliver load power. Quiescent power is simply the
the pins and the decoupling capacitors. Each
specified no-load supply current times the total supply
power-supply connection should always be
voltage across the part. P
DL
will depend on the
decoupled with one of these capacitors. An optional
required output signal and load; though, for resistive
supply decoupling capacitor (0.1 µ F) across the two
loads connected to mid-supply (V
S
/2), P
DL
is at a
power supplies (for bipolar operation) will improve
maximum when the output is fixed at a voltage equal
2nd-harmonic distortion performance. Larger (2.2 µ F
to V
S
/4 or 3V
S
/4. Under this condition, P
DL
= V
S
2
/(16
to 6.8 µ F) decoupling capacitors, effective at lower
× R
L
), where R
L
includes feedback network loading.
frequency, should also be used on the main supply
Note that it is the power in the output stage, and not pins. These may be placed somewhat farther from
into the load, that determines internal power the device and may be shared among several
dissipation. devices in the same area of the PC board.
As a worst-case example, compute the maximum T
J
c) Careful selection and placement of external
using an OPA2832 (MSOP-8 package) in the circuit components will preserve the high-frequency
of Figure 63 operating at the maximum specified performance. Resistors should be a very low
ambient temperature of +85 ° C and driving both reactance type. Surface-mount resistors work best
channels at a 150 Ω load at mid-supply. and allow a tighter overall layout. Metal film or carbon
composition axially-leaded resistors can also provide
good high-frequency performance. Again, keep their
leads and PCB traces as short as possible. Never
use wire-wound type resistors in a high-frequency
application. Since the output pin and inverting input
pin are the most sensitive to parasitic capacitance,
always position the series output resistor, if any, as
Although this is still well below the specified
close as possible to the output pin. Other network
maximum junction temperature, system reliability
components, such as noninverting input termination
considerations may require lower ensured junction
resistors, should also be placed close to the package.
temperatures. The highest possible internal
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