Datasheet

OPA2830
SBOS309D – AUGUST 2004 – REVISED AUGUST 2008 .................................................................................................................................................. www.ti.com
bandlimiting. To reduce unwanted capacitance, a d) Connections to other wideband devices on the
window around the signal I/O pins should be opened board may be made with short direct traces or
in all of the ground and power planes around those through onboard transmission lines. For short
pins. Otherwise, ground and power planes should be connections, consider the trace and the input to the
unbroken elsewhere on the board. next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
b) Minimize the distance ( < 0.25") from the
preferably with ground and power planes opened up
power-supply pins to high-frequency 0.1 µ F
around them. Estimate the total capacitive load and
decoupling capacitors. At the device pins, the ground
set R
S
from the typical characteristic curve
and power-plane layout should not be in close
Recommended R
S
vs Capacitive Load. Low parasitic
proximity to the signal I/O pins. Avoid narrow power
capacitive loads ( < 5pF) may not need an R
S
since
and ground traces to minimize inductance between
the OPA2830 is nominally compensated to operate
the pins and the decoupling capacitors. Each
with a 2pF parasitic load. Higher parasitic capacitive
power-supply connection should always be
loads without an R
S
are allowed as the signal gain
decoupled with one of these capacitors. An optional
increases (increasing the unloaded phase margin). If
supply decoupling capacitor (0.1 µ F) across the two
a long trace is required, and the 6dB signal loss
power supplies (for bipolar operation) will improve
intrinsic to a doubly-terminated transmission line is
2nd-harmonic distortion performance. Larger (2.2 µ F
acceptable, implement a matched impedance
to 6.8 µ F) decoupling capacitors, effective at lower
transmission line using microstrip or stripline
frequency, should also be used on the main supply
techniques (consult an ECL design handbook for
pins. These may be placed somewhat farther from
microstrip and stripline layout techniques). A 50 Ω
the device and may be shared among several
environment is normally not necessary onboard, and
devices in the same area of the PC board.
in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots.
c) Careful selection and placement of external
With a characteristic board trace impedance defined
components will preserve the high-frequency
(based on board material and trace dimensions), a
performance. Resistors should be a very low
matching series resistor into the trace from the output
reactance type. Surface-mount resistors work best
of the OPA2830 is used as well as a terminating
and allow a tighter overall layout. Metal film or carbon
shunt resistor at the input of the destination device.
composition axially-leaded resistors can also provide
Remember also that the terminating impedance will
good high-frequency performance. Again, keep their
be the parallel combination of the shunt resistor and
leads and PC board traces as short as possible.
the input impedance of the destination device; this
Never use wire-wound type resistors in a
total effective impedance should be set to match the
high-frequency application. Since the output pin and
trace impedance. If the 6dB attenuation of a
inverting input pin are the most sensitive to parasitic
doubly-terminated transmission line is unacceptable,
capacitance, always position the feedback and series
a long trace can be series-terminated at the source
output resistor, if any, as close as possible to the
end only. Treat the trace as a capacitive load in this
output pin. Other network components, such as
case and set the series resistor value as shown in the
noninverting input termination resistors, should also
typical characteristic curve Recommended R
S
vs
be placed close to the package. Where double-side
Capacitive Load. This will not preserve signal integrity
component mounting is allowed, place the feedback
as well as a doubly-terminated line. If the input
resistor directly under the package on the other side
impedance of the destination device is low, there will
of the board between the output and inverting input
be some signal attenuation due to the voltage divider
pins. Even with a low parasitic capacitance shunting
formed by the series output into the terminating
the external resistors, excessively high resistor values
impedance.
can create significant time constants that can
degrade performance. Good axial metal film or
e) Socketing a high-speed part is not
surface-mount resistors have approximately 0.2pF in
recommended. The additional lead length and
shunt with the resistor. For resistor values > 1.5k Ω ,
pin-to-pin capacitance introduced by the socket can
this parasitic capacitance can add a pole and/or zero
create an extremely troublesome parasitic network
below 500MHz that can effect circuit operation. Keep
which can make it almost impossible to achieve a
resistor values as low as possible consistent with
smooth, stable frequency response. Best results are
load driving considerations. The 750 Ω feedback used
obtained by soldering the OPA2830 onto the board.
in the Typical Characteristics is a good starting point
for design.
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