Datasheet

THERMAL ANALYSIS
E
N
+ E
NI
2
)
ǒ
I
BN
R
S
Ǔ
2
) 4kTR
S
)
ǒ
I
BI
R
F
NG
Ǔ
2
)
4kTR
F
NG
Ǹ
(2)
DC ACCURACY AND OFFSET CONTROL
P
D
+ 10V 11.9mA ) 2
ƪ
5
2
ǒ
16
ǒ
150W ø 1500W
ǓǓ
ƫ
+ 142mW
Maximum T
J
+ ) 85
o
C )
ǒ
0.142W 150
o
CńW
Ǔ
+ 106
o
C
BOARD LAYOUT GUIDELINES
OPA2830
www.ti.com .................................................................................................................................................. SBOS309D – AUGUST 2004 – REVISED AUGUST 2008
Dividing this expression by the noise gain
(NG = (1 + R
F
/R
G
)) will give the equivalent
Maximum desired junction temperature will set the
input-referred spot noise voltage at the noninverting
maximum allowed internal power dissipation, as
input, as shown in Equation 2 :
described below. In no case should the maximum
junction temperature be allowed to exceed +150 ° C.
Operating junction temperature (T
J
) is given by
T
A
+ P
D
× θ
JA
. The total internal power dissipation
Evaluating these two equations for the circuit and
(P
D
) is the sum of quiescent power (P
DQ
) and
component values shown in Figure 70 will give a total
additional power dissipated in the output stage (P
DL
)
output spot noise voltage of 19.3nV/ √ Hz and a total
to deliver load power. Quiescent power is simply the
equivalent input spot noise voltage of 9.65nV/ √ Hz.
specified no-load supply current times the total supply
This is including the noise added by the resistors.
voltage across the part. P
DL
will depend on the
This total input-referred spot noise voltage is not
required output signal and load; though, for resistive
much higher than the 9.2nV/ √ Hz specification for the
loads connected to mid-supply (V
S
/2), P
DL
is at a
op amp voltage noise alone.
maximum when the output is fixed at a voltage equal
to V
S
/4 or 3V
S
/4. Under this condition, P
DL
= V
S
2
/(16
× R
L
), where R
L
includes feedback network loading.
The balanced input stage of a wideband Note that it is the power in the output stage, and not
voltage-feedback op amp allows good output DC into the load, that determines internal power
accuracy in a wide variety of applications. The dissipation.
power-supply current trim for the OPA2830 gives
As a worst-case example, compute the maximum T
J
even tighter control than comparable products.
using an OPA2830 (MSOP-8 package) in the circuit
Although the high-speed input stage does require
of Figure 72 operating at the maximum specified
relatively high input bias current (typically 5 µ A out of
ambient temperature of +85 ° C and driving a 150 Ω
each input terminal), the close matching between
load at +2.5V
DC
on both outputs.
them may be used to reduce the output DC error
caused by this current. This is done by matching the
DC source resistances appearing at the two inputs.
Evaluating the configuration of Figure 72 (which has
matched DC input resistances), using worst-case
+25 ° C input offset voltage and current specifications,
gives a worst-case output offset voltage equal to:
• (NG = noninverting signal gain at DC)
Although this is still well below the specified
• ± (NG × V
OS(MAX)
) + (R
F
× I
OS(MAX)
)
maximum junction temperature, system reliability
• = ± (2 × 7.5mV) נ (375 Ω × 1.1 µ A)
considerations may require lower ensured junction
• = ± 15.41mV
temperatures. The highest possible internal
dissipation will occur if the load requires current to be
A fine-scale output offset null, or DC operating point
forced into the output at high output voltages or
adjustment, is often required. Numerous techniques
sourced from the output at low output voltages. This
are available for introducing DC offset control into an
puts a high current through a large internal voltage
op amp circuit. Most of these techniques are based
drop in the output transistors.
on adding a DC current through the feedback
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal path
frequency response. If the signal path is intended to
Achieving optimum performance with a
be noninverting, the offset control is best applied as
high-frequency amplifier like the OPA2830 requires
an inverting summing signal to avoid interaction with
careful attention to board layout parasitics and
the signal source. If the signal path is intended to be
external component types. Recommendations that
inverting, applying the offset control to the
will optimize performance include:
noninverting input may be considered. Bring the DC
a) Minimize parasitic capacitance to any AC ground
offsetting current into the inverting input node through
for all of the signal I/O pins. Parasitic capacitance on
resistor values that are much larger than the signal
the output and inverting input pins can cause
path resistors. This will insure that the adjustment
instability: on the noninverting input, it can react with
circuit has minimal effect on the loop gain and hence
the source impedance to cause unintentional
the frequency response.
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