Datasheet

OUTPUT CURRENT AND VOLTAGES DISTORTION PERFORMANCE
NOISE PERFORMANCE
DRIVING CAPACITIVE LOADS
4kT
R
G
R
G
R
F
R
S
1/2
OPA2830
I
BI
E
O
I
BN
4kT = 1.6E
−
20J
at 290
_
K
E
RS
E
NI
4kTR
S
√
4kTR
F
√
E
O
+
ǒ
E
NI
2
)
ǒ
I
BN
R
S
Ǔ
2
) 4kTR
S
Ǔ
NG
2
)
ǒ
I
BI
R
F
Ǔ
2
) 4kTR
F
NGǸ
(1)
OPA2830
SBOS309D – AUGUST 2004 – REVISED AUGUST 2008 .................................................................................................................................................. www.ti.com
The OPA2830 provides outstanding output voltage The OPA2830 provides good distortion performance
capability. For the +5V supply, under no-load into a 150 Ω load. Relative to alternative solutions, it
conditions at +25 ° C, the output voltage typically provides exceptional performance into lighter loads
swings closer than 90mV to either supply rail. and/or operating on a single +3V supply. Generally,
until the fundamental signal reaches very high
The minimum specified output voltage and current
frequency or power levels, the 2nd-harmonic will
specifications over temperature are set by worst-case
dominate the distortion with a negligible 3rd-harmonic
simulations at the cold temperature extreme. Only at
component. Focusing then on the 2nd-harmonic,
cold startup will the output current and voltage
increasing the load impedance improves distortion
decrease to the numbers shown in the ensured
directly. Remember that the total load includes the
tables. As the output transistors deliver power, their
feedback network; in the noninverting configuration
junction temperatures will increase, decreasing their
(see Figure 72 ) this is sum of R
F
+ R
G
, while in the
V
BE
s (increasing the available output voltage swing)
inverting configuration, only R
F
needs to be included
and increasing their current gains (increasing the
in parallel with the actual load. Running differentially
available output current). In steady-state operation,
suppresses the 2nd-harmonic, as shown in the
the available output voltage and current will always
differential typical characteristic curves.
be greater than that shown in the over-temperature
specifications, since the output stage junction
temperatures will be higher than the minimum
specified operating ambient.
High slew rate, unity-gain stable, voltage-feedback op
amps usually achieve their slew rate at the expense
of a higher input noise voltage. The 9.2nV/ √ Hz input
voltage noise for the OPA2830 however, is much
One of the most demanding and yet very common
lower than comparable amplifiers. The input-referred
load conditions for an op amp is capacitive loading.
voltage noise and the two input-referred current noise
Often, the capacitive load is the input of an
terms (2.8pA/ √ Hz) combine to give low output noise
ADC — including additional external capacitance which
under a wide variety of operating conditions.
may be recommended to improve ADC linearity. A
Figure 85 shows the op amp noise analysis model
high-speed, high open-loop gain amplifier like the
with all the noise terms included. In this model, all
OPA2830 can be very susceptible to decreased
noise terms are taken to be noise voltage or current
stability and closed-loop response peaking when a
density terms in either nV/ √ Hz or pA/ √ Hz.
capacitive load is placed directly on the output pin.
When the primary considerations are frequency
response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is
to isolate the capacitive load from the feedback loop
by inserting a series isolation resistor between the
amplifier output and the capacitive load.
The Typical Characteristic curves show the
recommended R
S
versus capacitive load and the
resulting frequency response at the load. Parasitic
capacitive loads greater than 2pF can begin to
degrade the performance of the OPA2830. Long PC
board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
Figure 85. Noise Analysis Model
the output pin (see the Board Layout Guidelines
section).
The total output spot noise voltage can be computed
The criterion for setting this R
S
resistor is a maximum
as the square root of the sum of all squared output
bandwidth, flat frequency response at the load. For a
noise voltage contributors. Equation 1 shows the
gain of +2, the frequency response at the output pin
general form for the output noise voltage using the
is already slightly peaked without the capacitive load,
terms shown in Figure 85 :
requiring relatively high values of R
S
to flatten the
response at the load. Increasing the noise gain will
also reduce the peaking (see Figure 77 ).
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