Datasheet

INVERTING AMPLIFIER OPERATION
1/2
OPA2830
50
Ω
Source
R
F
750
Ω
R
G
374
Ω
2R
T
1.5k
Ω
R
M
57.6
Ω
+5V
2R
T
1.5k
Ω
150
Ω
0.1
µ
F 6.8
µ
F
+
0.1
µ
F
0.1
µ
F
+V
S
2
OPA2830
www.ti.com .................................................................................................................................................. SBOS309D – AUGUST 2004 – REVISED AUGUST 2008
Frequency response in a gain of +2 may be modified signal channel input impedance. If input impedance
to achieve exceptional flatness simply by increasing matching is desired (which is beneficial whenever the
the noise gain to 3. One way to do this, without signal is coupled through a cable, twisted pair, long
affecting the +2 signal gain, is to add an 2.55k Ω PC board trace, or other transmission line conductor),
resistor across the two inputs, as shown in Figure 77 . R
G
may be set equal to the required termination value
A similar technique may be used to reduce peaking in and R
F
adjusted to give the desired gain. This is the
unity-gain (voltage follower) applications. For simplest approach and results in optimum bandwidth
example, by using a 750 Ω feedback resistor along and noise performance.
with a 750 Ω resistor across the two op amp inputs,
However, at low inverting gains, the resulting
the voltage follower response will be similar to the
feedback resistor value can present a significant load
gain of +2 response of Figure 71 . Further reducing
to the amplifier output. For an inverting gain of 2,
the value of the resistor across the op amp inputs will
setting R
G
to 50 Ω for input matching eliminates the
further dampen the frequency response due to
need for R
M
but requires a 100 Ω feedback resistor.
increased noise gain. The OPA2830 exhibits minimal
This configuration has the interesting advantage of
bandwidth reduction going to single-supply (+5V)
the noise gain becoming equal to 2 for a 50 Ω source
operation as compared with ± 5V. This minimal
impedance — the same as the noninverting circuits
reduction is because the internal bias control circuitry
considered above. The amplifier output will now see
retains nearly constant quiescent current as the total
the 100 Ω feedback resistor in parallel with the
supply voltage between the supply pins is changed.
external load. In general, the feedback resistor should
be limited to the 200 Ω to 1.5k Ω range. In this case, it
is preferable to increase both the R
F
and R
G
values,
as shown in Figure 84 , and then achieve the input
All of the familiar op amp application circuits are
matching impedance with a third resistor (R
M
) to
available with the OPA2830 to the designer. See
ground. The total input impedance becomes the
Figure 84 for a typical inverting configuration where
parallel combination of R
G
and R
M
.
the I/O impedances and signal gain from Figure 70
are retained in an inverting circuit configuration.
The second major consideration, touched on in the
Inverting operation is one of the more common
previous paragraph, is that the signal source
requirements and offers several performance
impedance becomes part of the noise gain equation
benefits. It also allows the input to be biased at V
S
/2
and hence influences the bandwidth. For the example
without any headroom issues. The output voltage can
in Figure 84 , the R
M
value combines in parallel with
be independently moved to be within the output
the external 50 Ω source impedance (at high
voltage range with coupling capacitors, or bias
frequencies), yielding an effective driving impedance
adjustment resistors.
of 50 Ω || 57.6 Ω = 26.8 Ω . This impedance is added in
series with R
G
for calculating the noise gain. The
resulting noise gain is 2.87 for Figure 84 , as opposed
to only 2 if R
M
could be eliminated as discussed
above. The bandwidth will therefore be lower for the
gain of – 2 circuit of Figure 84 (NG = +2.87) than for
the gain of +2 circuit of Figure 70 .
The third important consideration in inverting amplifier
design is setting the bias current cancellation
resistors on the noninverting input (a parallel
combination of R
T
= 750 Ω ). If this resistor is set equal
to the total DC resistance looking out of the inverting
node, the output DC error, due to the input bias
currents, will be reduced to (Input Offset Current)
times R
F
. With the DC blocking capacitor in series
with R
G
, the DC source impedance looking out of the
inverting mode is simply R
F
= 750 Ω for Figure 84 . To
reduce the additional high-frequency noise introduced
by this resistor and power-supply feed-through, R
T
is
bypassed with a capacitor.
Figure 84. AC-Coupled, G = – 2 Example Circuit
In the inverting configuration, three key design
considerations must be noted. The first consideration
is that the gain resistor (R
G
) becomes part of the
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