Datasheet

R
R
F
402W
R
G
402W
R
F
402W
R
G
402W
V
IN
V
OUT
R
1/2
OPA2690
OPA692
C
C
1/2
OPA2690
OPA2690
www.ti.com SBOS238G –JUNE 2002–REVISED MARCH 2010
Typically, channel switching is performed either on Each of the two filter stages is a 1st-order filter with a
sync or retrace time in the video signal. The two voltage gain of +1. The delay time through one filter
inputs are approximately equal at this time. The is given by Equation 3:
make-before-break disable characteristic of the
t
GR0
= 2RC (3)
OPA2690 ensures that there is always one amplifier
For a more accurate analysis of the circuit, consider
controlling the line when using a wired-OR circuit like
the group delay for the amplifiers. For example, in the
that shown in Figure 41. As both inputs may be on for
case of the OPA2690, the group delay in the
a short period during the transition between channels,
bandwidth from 1MHz to 100MHz is approximately
the outputs are combined through the output
1.0ns. To account for this, modify the transfer
impedance matching resistors (82.5Ω in this case).
function, which now comes out to be:
When one channel is disabled, its feedback network
t
GR
= 2(2RC + t
D
) (4)
forms part of the output impedance and slightly
attenuates the signal in getting out onto the cable.
Where t
D
= (1/360) × (df/df) = delay of the op amp
The gain and output matching resistor have been
itself.
slightly increased to get a signal gain of +1 at the
matched load and provide a 75Ω output impedance to The values of resistors R
F
and R
G
should be equal
the cable. The video multiplexer connection (see and low to avoid parasitic effects. If the all-pass filter
Figure 41) also ensures that the maximum differential is designed for very low delay times, include parasitic
voltage across the inputs of the unselected channel board capacitances to calculate the correct delay
does not exceed the rated ±1.2V maximum for time. Simulating this application using the PSPICE
standard video signal levels. model of the OPA2690 will allow this design to be
tuned to the desired performance.
See the Disable Operation section for the turn-on and
turn-off switching glitches using a 0V input for a
DIFFERENTIAL RECEIVER/DRIVER
single channel is typically less than ±50mV. Where
two outputs are switched (see Figure 41), the output
A very versatile application for a dual operational
line is always under the control of one amplifier or the
amplifier is the differential amplifier configuration
other due to the make-before-break disable timing. In
detailed in Figure 43. With both amplifiers of the
this case, the switching glitches for two 0V inputs
OPA2690 connected for noninverting operation, the
drops to < 20mV.
circuit provides a high input impedance whereas the
gain can easily be set by just one resistor, R
G
. When
HIGH-SPEED DELAY CIRCUIT operated in low gains, the output swing may be
limited as a result of the common-mode input swing
The OPA2690 makes an ideal amplifier for a variety
limits of the amplifier itself. An interesting modification
of active filter designs. Shown in Figure 42 is a circuit
of this circuit is to place a capacitor in series with the
that uses the two amplifiers within the dual OPA2690
R
G
. Now the dc gain for each side is reduced to +1,
to design a two-stage analog delay circuit. For
whereas the ac gain still follows the standard transfer
simplicity, the circuit uses a dual-supply (±5V)
function of G = 1 + 2R
F
/R
G
. This might be
operation, but it can also be modified to operate on a
advantageous for applications processing only a
signal supply. The input to the first filter stage is
frequency band that excludes dc or very low
driven by the OPA692 wideband buffer amplifier to
frequencies. An input dc voltage resulting from input
isolate the signal input from the filter network.
bias currents is not amplified by the ac gain and can
be kept low. This circuit can be used as a differential
line receiver, driver, or as an interface to a differential
input ADC.
Figure 42. Two-Stage, All-Pass Network
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Product Folder Link(s): OPA2690