Datasheet

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SBOS270C − AUGUST 2003 − REVISED AUGUST 2008
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25
46k
Ω
60k
Ω
1.2V
120k
Ω
Control
−
V
S
+V
S
A0 or A1
−
V
S
Q1Q2
Figure 15. Supply Power Control Circuit
The shutdown feature for the OPA2674 is a positive-sup-
ply referenced, current-controlled interface. Open-collec-
tor (or drain) interfaces are most effective, as long as the
controlling logic can sustain the resulting voltage (in open
mode) that appears at the A0 or A1 pins. The A0/A1 pin
voltage is one diode below the positive supply voltage ap-
plied to the OPA2674 if the logic interface is open. For volt-
age output logic interfaces, the on/off voltage levels de-
scribed in the Electrical Characteristics apply only for
either the +6V used for the ±6V specifications or the +5V
for the single-supply specifications. An open-drain inter-
face is recommended to operate the A1 and A0 pins using
a higher positive supply and/or logic families with inade-
quate high-level voltage swings.
THERMAL ANALYSIS
Due to the high output power capability of the OPA2674,
heat-sinking or forced airflow may be required under ex-
treme operating conditions. Maximum desired junction
temperature sets the maximum allowed internal power dis-
sipation, described below. In no case should the maximum
junction temperature be allowed to exceed 150°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
×
q
JA
. The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipation in
the output stage (P
DL
) to deliver load power. Quiescent
power is the specified no-load supply current times the to-
tal supply voltage across the part. P
DL
depends on the re-
quired output signal and load. Using the example power
calculation for the ADSL CPE line driver concluded in
Equation 13, and a worst-case analysis at +70°C ambient,
the maximum internal junction temperature for the SO-8
package will be:
T
J MAX
= T
AMBIENT
+ P
MAX
× 125°C/W
T
J MAX
= 70°C + ((12V × 18.8mA) + 12V × 128mA/(5.33)
− 40mW) × 125°C/W = 129°C
This maximum junction temperature is well below the max-
imum of 150°C but may exceed system design targets.
Lower junction temperature would be possible using the
SO-14 package and the power cutback feature. Repeating
this calculation for that solution gives:
T
J MAX
= 70°C + ((12V × 14.2mA) + 12V × 128mA/(5.33)
− 40mW) × 100°C/W = 112°C
For extremely high internal power applications, where im-
proved thermal performance is required, consider the
PSO-8 package of the OPA2677—a similar part with no
output stage current limit and a thermal impedance of less
than 50°C/W.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency
amplifier like the OPA2674 requires careful attention to
board layout parasitic and external component types. Rec-
ommendations that optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the out-
put and inverting input pins can cause instability; on the
noninverting input, it can react with the source impedance
to cause unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25″) from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 8 for an SO-8 package) should
always be decoupled with these capacitors. An optional
supply decoupling capacitor across the two power supplies
(for bipolar operation) improves 2nd-harmonic distortion per-
formance. Larger (2.2µF to 6.8µF) decoupling capacitors,
effective at a lower frequency, should also be used on the
main supply pins. These can be placed somewhat farther
from the device and may be shared among several de-
vices in the same area of the PC board.
c) Careful selection and placement of external compo-
nents preserve the high-frequency performance of the
OPA2674. Resistors should be of a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially
leaded resistors can also provide good high-frequency
performance. Again, keep the leads and PCB trace length
as short as possible. Never use wire-wound type resistors
in a high-frequency application. Although the output pin
and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series out-
put resistor, if any, as close as possible to the output pin.
Other network components, such as noninverting input
termination resistors, should also be placed close to the
package. Where double-side component mounting is al-
lowed, place the feedback resistor directly under the pack-