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BOARD LAYOUT GUIDELINES
1/2
OPA2652
V
V
O
I
R
R
F
G
= = 2- -
R
F
1kW
±200mVOutputAdjustment
SupplyDecoupling
NotShown
5kW
5kW
328W
0.1 Fm
R
G
500W
V
I
20kW
10kW
0.1 Fm
-5V
+5V
+5V
-5V
V
O
Thermal Analysis
OPA2652
SBOS125A – JUNE 2000 – REVISED MAY 2006
This absolute worst-case condition meets the
specified maximum junction temperature. Actual P
DL
will almost always be less than that considered here.
Carefully consider maximum T
J
in your application.
Achieving optimum performance with a
high-frequency amplifier such as the OPA2652
requires careful attention to board layout parasitics
and external component types. Recommendations
that will optimize performance include:
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it can
react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins
Figure 36. DC-Coupled, Inverting Gain of –2, with
should be opened in all of the ground and power
Offset Adjustment
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b) Minimize the distance (< 0.25") from the
Heatsinking or forced airflow may be required under
power-supply pins to high-frequency 0.1 µ F
extreme operating conditions. Maximum desired
decoupling capacitors. At the device pins, the ground
junction temperature will set the maximum allowed
and power plane layout should not be in close
internal power dissipation as described below. In no
proximity to the signal I/O pins. Avoid narrow power
case should the maximum junction temperature be
and ground traces to minimize inductance between
allowed to exceed 175 ° C.
the pins and the decoupling capacitors. The
Operating junction temperature (T
J
) is given by T
A
+
power-supply connections should always be
P
D
• θ
JA
. The total internal power dissipation (P
D
) is
decoupled with these capacitors. An optional supply
the sum of quiescent power (P
DQ
) and additional
decoupling capacitor (0.1 µ F) across the two power
power dissipated in the output stage (P
DL
) to deliver
supplies (for bipolar operation) will improve 2nd
load power. Quiescent power is simply the specified
harmonic distortion performance. Larger (2.2 µ F to
no-load supply current times the total supply voltage
6.8 µ F) decoupling capacitors, effective at lower
across the part. P
DL
depends on the required output
frequency, should also be used on the main supply
signal and load; for a grounded resistive load, P
DL
is
pins. These capacitors may be placed somewhat
at a maximum when the output is fixed at a voltage
farther from the device and may be shared among
equal to 1/2 of either supply voltage (for equal
several devices in the same area of the PCB.
bipolar supplies). Under this condition, P
DL
=
c) Careful selection and placement of external
V
S
2
/(4 • R
L
) where R
L
includes feedback network
components will preserve the high frequency
loading.
performance of the OPA2652. Resistors should be
Note that it is the power in the output stage, and not
a very low reactance type. Surface-mount resistors
into the load, that determines internal power
work best and allow a tighter overall layout. Metal
dissipation.
film or carbon composition axiallyleaded resistors
can also provide good high frequency performance.
As an example, compute the maximum T
J
using an
Again, keep resistor leads and PCB traces as short
OPA2652E (SOT23-8 package) in the circuit of
as possible. Never use wirewound type resistors in a
Figure 28 operating at the maximum specified
high-frequency application. Since the output pin and
ambient temperature of +85 ° C and with both outputs
inverting input pin are the most sensitive to parasitic
driving 2.5V
DC
into a grounded 100 Ω load.
capacitance, always position the feedback and series
P
D
= 10V • 15.5mA + 2 [5
2
/(4 • [100 Ω 804 Ω ])] =
output resistor, if any, as close as possible to the
296mW
output pin. Other network components, such as
noninverting input termination resistors, should also
Maximum T
J
= +85 ° C + (0.30W • 150 ° C/W) = 130 ° C
be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side
16
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