Datasheet

®
OPA21119
APPLICATIONS CIRCUITS
Figures 5 through 13 are circuit diagrams of various appli-
cations for the OPA2111.
GUARDING AND SHIELDING
As in any situation where high impedances are involved,
careful shielding is required to reduce “hum” pickup in input
leads. If large feedback resistors are used, they should also
be shielded along with the external input circuitry.
Leakage currents across printed circuit boards can easily
exceed the bias current of the OPA2111. To avoid leakage
problems, it is recommended that the signal input lead of the
OPA2111 be wired to a Teflon standoff. If the OPA2111 is
to be soldered directly into a printed circuit board, utmost
care must be used in planning the board layout. A “guard”
pattern should completely surround the high impedance
input leads and should be connected to a low impedance
point which is at the signal input potential (see Figure 2).
NOISE: FET vs BIPOLAR
Low noise circuit design requires careful analysis of all
noise sources. External noise sources can dominate in many
cases, so consider the effect of source resistance on overall
operational amplifier noise performance. At low source
impedances, the low voltage noise of a bipolar operational
amplifier is superior, but at higher impedances the high
current noise of a bipolar amplifier becomes a serious
liability. Above about 15kΩ the OPA2111 will have lower
total noise than an OP-27 (see Figure 3).
BIAS CURRENT CHANGE
vs COMMON-MODE VOLTAGE
The input bias currents of most popular BIFET® opera-
tional amplifiers are affected by common-mode voltage
(Figure 4). Higher input FET gate-to-drain voltage causes
leakage and ionization (bias) currents to increase. Due to its
cascode input stage, the extremely low bias current of the
OPA2111 is not compromised by common-mode voltage.
FIGURE 2. Connection of Input Guard. FIGURE 5. Auto-Zero Amplifier.
FIGURE 3. Voltage Noise Spectral Density vs Source
Resistance.
FIGURE 4. Input Bias Currrent vs Common-Mode Voltage.
Out
10kΩ
1MΩ
1
2
3
7
6
5
1/2 
OPA2111BM
100kΩ
In
1µF
Polypropylene
100kΩ
100Ω
1/2 
OPA2111BM
Operate
Zero
Gain = –100
V
OS
≤ 5µV
Drift ≤ 0.028µV/°C
Zero Droop ≤ 2µV/s
Referred to Input
100 1k 10k 100k 1M 10M
1k
100
10
Voltage Noise Spectral Density (E
O
)
Typical at 1kHz (nV/ Hz)
BM
OP-27 + Resistor
OPA2111 + Resistor
Resistor Noise Only
OPA2111 + Resistor
Resistor Noise Only
OP-27 + Resistor
E
O
R
S
1
Source Resistance, R
S
(Ω)
E
O
= e
N
2
+ (i
N
R
S
)
2
+ 4kTR
S
80
60
40
20
0
–15
–10 –5 0 5 10 15
Common-Mode Voltage (VDC)
Input Bias Current (pA)
OP-15/16/17 “Perfect Bias Current Cancellation”
AD547
LF156/157
LF155
T
A
= 25°C; curves taken from
manufacturers' published
typical data
OPA2111
–20
2
3
1
In
Out
Inverting TO-99 Bottom View
2
3
1
In
Out
Non-Inverting
2
3
1
In
Out
Buffer
Board layout for input guarding: guard top and bottom of board.
Alternate: use Teflon
®
standoff for sensitive input pins.
Teflon
®
E. I. Du Pont de Nemours & Co.
A
A
A
4
7
8
1
3
2
5
6