Datasheet
9
®
OPA111
should completely surround the high impedance input leads
and should be connected to a low impedance point which is
at the signal input potential.
The amplifier case should be connected to any input shield
or guard via pin 8. This insures that the amplifier itself is
fully surrounded by guard potential, minimizing both leak-
age and noise pickup (see Figure 3).
If guarding is not required, pin 8 (case) should be connected
to ground.
FIGURE 4. Voltage Noise Spectral Density vs Source
Resistance.
FIGURE 6. Pyroelectric Infrared Detector.
FIGURE 3. Connection of Input Guard.
NOISE: FET VERSUS BIPOLAR
Low noise circuit design requires careful analysis of all
noise sources. External noise sources can dominate in many
cases, so consider the effect of source resistance on overall
operational amplifier noise performance. At low source
impedances, the lower voltage noise of a bipolar operational
amplifier is superior, but at higher impedances the high
current noise of a bipolar amplifier becomes a serious
liability. Above about 15kΩ, the OPA111 will have a lower
total noise than an OP-27 (see Figure 4).
BIAS CURRENT CHANGE
VERSUS COMMON-MODE VOLTAGE
The input bias current of most popular BIFET operational
amplifiers are affected by common-mode voltage (Figure 5).
Higher input FET gate-to-drain voltage causes leakage and
ionization (bias) currents to increase. Due to its cascode
input stage, the extremely low bias current of the OPA111 is
not compromised by common-mode voltage.
APPLICATIONS CIRCUITS
Figures 6 through 18 are circuit diagrams of various appli-
cations for the OPA111.
FIGURE 5. Input Bias Currrent vs Common-Mode Voltage.
80
60
40
20
0
–20
–15
–10 –5 0 5 10 15
Common-Mode Voltage (VDC)
Input Bias Current (pA)
OPA111
AD547
LF156/157
LF155
T
A
= 25°C; curves taken from
manufacturers' published
typical data.
OP-15/16/17
"Perfect Bias Current Cancellation"
OPA111
2
3
6
Output
8
1000pF Polystyrene
1000MΩ
1000MΩ
Pyroelectric
Detector
NOTE: Pyroelectric
detectors respond
to rate-of-change
(AC signal) only.
3
2
4
5
6
7
8
1
OPA111
2
3
6
8
In
Out
Inverting TO-99 Bottom View
OPA111
2
3
6
In
Out
Non-Inverting
8
OPA111
2
3
6
In
Out
Buffer
8
Board layout for input guarding: guard top and bottom of board.
Alternate: use Teflon
®
standoff for sensitive input pins.
Teflon
®
E. I. Du Pont de Nemours & Co.
100 1k 10k 100k 1M 10M
1k
100
10
1
Voltage Noise Spectral Density, E
O
Hz)Typical at 1kHz (nV/
BM
OP-27 + Resistor
OPA111 + Resistor
Resistor Noise Only
OPA111 + Resistor
Resistor Noise Only
OP-27 + Resistor
Source Resistance, R
S
(Ω)
E
O
R
S
E
O
= e
N
2
+ (I
N
R
S
)
2
+ 4kTR
S