Datasheet

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PACKAGE
ONET4211LD
SLLS688A NOVEMBER 2005 REVISED SEPTEMBER 2007
Table 1. Response to I/O-Pin Shorts to VCC or GND
FLTMODE = LOW FLTMODE = HIGH
PIN
Response to Short to GND Response to Short to V
CC
Response to Short to GND Response to Short to V
CC
APCSET SDOWN latched high, I
BIAS
and No fault, I
MOD
unaffected SDOWN high, I
BIAS
and I
MOD
No fault
I
MOD
disabled unaffected
BIAS SDOWN latched high, I
MOD
No fault, I
BIAS
goes to zero SDOWN high, I
MOD
No fault, I
MOD
unaffected
disabled unaffected
CAPC No fault No fault, I
BIAS
goes to zero No fault, I
MOD
unaffected No fault, I
BIAS
goes to zero
DIN+ No fault, I
MOD
disabled No fault No fault, I
MOD
disabled No fault
DIN No fault, I
MOD
disabled No fault No fault, I
MOD
disabled No fault
DISABLE Normal circuit operation Normal circuit operation Normal circuit operation Normal circuit operation
IBMAX SDOWN latched high, I
BIAS
and SDOWN latched high, I
BIAS
SDOWN high, I
MOD
SDOWN high, I
MOD
unaffected
I
MOD
disabled and I
MOD
disabled unaffected
MOD+ SDOWN latched high, I
BIAS
and No fault SDOWN high, I
BIAS
No fault
I
MOD
disabled unaffected
MOD SDOWN latched high, I
BIAS
and No fault SDOWN high, I
BIAS
No fault
I
MOD
disabled unaffected
MODSET SDOWN latched high, I
BIAS
and No fault, I
MOD
disabled SDOWN high, I
BIAS
No fault, I
MOD
disabled
I
MOD
disabled unaffected
MODTC SDOWN latched high, I
BIAS
and No fault SDOWN high, I
BIAS
and I
MOD
No fault
I
MOD
disabled unaffected
MONB No fault SDOWN latched high, I
BIAS
No fault SDOWN high, I
BIAS
and I
MOD
and I
MOD
disabled unaffected
MONP No fault SDOWN latched high, I
BIAS
No fault SDOWN high, I
BIAS
and I
MOD
and I
MOD
disabled unaffected
OUTPOL No fault, polarity reverses No fault No fault, polarity reverses No fault
PD No fault, I
MOD
unaffected No fault, I
BIAS
goes to zero No fault, I
MOD
unaffected No fault, I
BIAS
goes to zero
SDOWN No fault No fault No fault No fault
For the ONET4211LD, a small-footprint, 4-mm × 4-mm, 24-lead QFN package is used, with a lead pitch of 0,5
mm. The pinout is shown in Figure 3 .
To achieve the required low thermal resistance of about 38 K/W, which keeps the maximum junction temperature
below 115 ° C, a good thermal connection of the exposed die pad is mandatory.
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