MSP50C614 Mixed-Signal Processor User’s Guide SPSU014 January 2000 Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
Preface Read This First About This Manual This user’s guide gives information for the MSP50C61 mixed-signal processor. This information includes a functional overview, a detailed architectural description, device peripheral functional description, assembly language instruction listing, code development tools, applications, customer information, and electrical characteristics (in data sheet).
Notational Conventions version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing: 0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .
Information About Cautions and Warnings Unless the list is enclosed in square brackets, you must choose one item from the list. - Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this directive is: .byte value1 [, ... , valuen ] This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas.
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Contents Contents 1 Introduction to the MSP50C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Features of the C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Development Device: MSP50P614 . . . . . . . . . . . . . . .
Contents 3.2 3.3 3.4 3.5 4 viii 3.1.1 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 Dedicated Input Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.3 Dedicated Output Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.4 Branch on D Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 5 4.4.8 Class 8 Instructions: Logic and Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 4.4.9 Class 9 Instructions: Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 Bit, Byte, Word and String Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 MSP50P614/MSP50C614 Computational Modes . . . . . . . . . . . . . . . . . . . . . . .
Contents 5.10 5.11 5.12 5.9.10 String Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.11 Constant Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10.1 Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents B.4 C B.3.5 Host Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.6 Host Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.3.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures Figures 1–1 1–2 1–3 1–4 1–5 Functional Block Diagram for the C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Oscillator and PLL Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 RESET Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 MSP50C614 100 Pin PJM PLastic Package Pinout . . . . . . . . . . . .
Figures 5–9 5–10 5–11 5–12 5–13 5–14 5–15 5–16 5–17 5–18 5–19 5–20 5–21 5–22 5–23 5–24 5–25 5–26 5–27 5–28 5–29 5–30 5–31 Select Program Folder Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Copying Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup Complete Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables Tables 1–1 1–2 Signal and Pad Descriptions for the C614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 MSP50C614 100-Pin PJM Plastic Package Pinout Description . . . . . . . . . . . . . . . . . . . . . 1-11 2–1 2–2 2–3 2–4 2–5 2–6 Signed and Unsigned Integer Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Summary of C614’s Peripheral Communications Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables 4–25 4–26 4–27 4–28 4–29 4–30 4–31 4–32 4–33 4–34 4–35 4–36 4–37 4–38 4–39 4–40 4–41 4–42 4–43 4–44 4–45 4–46 4–47 4–48 Class 4d Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 5 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 5 Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes, Cautions, and Warnings Notes, Cautions, and Warnings MSP50C605 and MSP50C604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 ROM Locations that Hold Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction to the MSP50C614 The MSP50C614 (C614) is a low cost, mixed signal controller, that combines a speech synthesizer, general-purpose I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new DSP which gives the C614 unprecedented speed and computational flexibility compared with previous devices of its type.
Features of the C614 1.
Applications 1.
Development Device: MSP50P614 1.3 Development Device: MSP50P614 The MSP50P614 is an EPROM based version of the MSP50C614, and is available in 120 pin windowed ceramic pin grid array. This EPROM based version of the device is only available in limited quantities to support software development. Since the MSP50P614 program memory is EPROM, each person doing software development should have several of these PGA packaged devices.
Functional Description 1.4 Functional Description The device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 64 bits of partially configurable I/O. The core processor is a general-purpose 16 bit micro-controller with DSP capability.
C605 and C604 (Preliminary Information) built in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The block diagram appearing in Figure 1–1 gives an overview of the C614 functionality. IMPORTANT: a one bit comparator is not currently supported. Typical connections to implement reset functionality are shown in Figure 1–3. 1.5 C605 and C604 (Preliminary Information) Two related products, the MSP50C605 (C605) and MSP50C604(C604) use the C614 core.
C605 and C604 (Preliminary Information) Figure 1–1. Functional Block Diagram for the C614 SCANIN SCANOUT SCANCLK Scan Interface Break Point Emulation OTP Program Serial Comm. SYNC TEST (C614 only) PGMPULSE (P614 only) VSS VDD 5 5 Power VPP (P614 only) (EP)ROM 32k x (16 + 1) bit Test-Area (reserved) 0x0000 to 0x07FF User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF DAC DACM 32 Ohm PDM RESET Initialization Logic 0x30 Instr.
C605 and C604 (Preliminary Information) Figure 1–2. Oscillator and PLL Connection a) Crystal Oscillator Operation Connections MSP50P614 MSP50C614 OSCIN OSCOUT PLL 10 MΩ† 32.768 kHz† 10 MΩ† 22 pF† 22 pF† C(PLL) = 3300 pF† † Keep these components as close as possible to the OSCIN, OSCOUT, and PLL pins.
C605 and C604 (Preliminary Information) Figure 1–3. RESET Circuit (MSP50P614 only) To Pin 1 of Optional (Scanport) Connector IN914‡ VPP 5V VDD 100 kΩ RESET Inside the MSP50P614 MSP50C614 IN914 1 kΩ† 1 µF (20%) Reset Switch To Pin 2 of optional (scan port) connector† VSS † If it is necessary to use the software development tools to control the MSP50P614 in application board, the 1 kΩ resistor is needed to allow the development tool to over drive the RESET circuit on the application board.
Terminal Assignments and Signal Descriptions 1.6 Terminal Assignments and Signal Descriptions Table 1–1.
Terminal Assignments and Signal Descriptions The C614 is sold in die form for its volume production. Contact you local TI sales office for mount and bond information. MSP50C614 is also available in 100 pin plastic QFP package. The pinout is shown in Figure 1–4 and Table 1–2. Table 1–2.
Terminal Assignments and Signal Descriptions Figure 1–4.
Terminal Assignments and Signal Descriptions For software development and prototyping, a windowed ceramic 120-pin grid array packaged P614 is available. The P614’s PGA package is shown in Figure 1–5 and Table 1–3: Figure 1–5.
Terminal Assignments and Signal Descriptions The pin assignments for the 120-pin PGA package (P614 device only) are outlined in the following table. Refer to Section 1.6 for more information on the signal functions.
Chapter 2 MSP50C614 Architecture A detailed description of MSP50C614 architecture is included in this chapter. After reading this chapter, the reader will have in-depth knowledge of internal blocks, memory organization, interrupt system, timers, clock control mechanism, and various low power modes. Topic Page 2.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 2.2 Computation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Architecture Overview The core processor in the C614 is a medium performance mixed signal processor with enhanced microcontroller features and a limited DSP instruction set. In addition to its basic multiply/accumulate structure for DSP routines, the core provides for a very efficient handling of string and bit manipulation. A unique accumulator-register file provides additional scratch pad memory and minimizes memory thrashing for many operations.
Figure 2–1.
Figure 2–2. Computational Unit Block Diagram (The shaded boxes represent internal programmable registers.
Computation Unit 2.2 Computation Unit The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’s algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram of the CU is shown in Figure 2–2. The multiplier block is served by 4 system registers: a 16-bit multiplier register (MR), a 16-bit write-only multiplicand register, a 16-bit high word product register (PH), and a 4-bit shift value register (SV).
Computation Unit The multiplicand source can be either data memory, an accumulator, or an accumulator offset. The multiplier source can be either the 16-bit multiplier register (MR) or the 4-bit shift value (SV) register. For all multiply operations, the MR register stores the multiplier operand. For barrel shift instructions, the multiplier operand is a 4-to-16-bit value that is decoded from the 4-bit shift value register (SV). Refer to Figure 2–4.
Computation Unit Figure 2–3. Overview of the Multiplier Unit Operation MULTIPLIER UNIT INPUTS Multiplicand 16-bit X Multiplier - latched in a write-only register from one of the following sources ... Data Memory Accumulator Offset Accumulator - writeable and readable by Data Memory as one of the following ...
Computation Unit The all-zero values are necessary for data transfers and unitary operations. All-zeros also serve as default values for the registers, which helps to minimize residual power consumption. The databus path through ALU-A is used to input memory values (RAM) and constant values (program memory) to the ALU. The PH and PL inputs are useful for supporting multiply-accumulate operations (refer to Section 2.2.1, Multiplier).
Computation Unit Figure 2–4. Overview of the Arithmetic Logic Unit ALU INPUTS ALU-A 16-bit ALU-B 16-bit - selects between ... (PH) (PL) - selects between ... all 0’s Offset Accumulator Register Data Memory Program Memory Product High† Product Low† all 0’s Accumulator Register ARITHMETIC LOGIC UNIT performs arithmetic, comparison, and logic ALU OUTPUTS THE ACCUMULATOR BLOCK Accumulator Register OFFSET Accumulator Register 16, 16-bit registers ... 16, 16-bit registers ...
Computation Unit When writing an accumulator-referenced instruction, therefore, the working accumulator address is stored in one of AP0 to AP3. The C614 instruction set provides a two-bit field for all accumulator referenced instructions. The two-bit field serves as a reference to the accumulator pointer which, in turn, stores the address of the actual 16-bit accumulator. Some MOV instructions store the contents of the APn directly to memory or load from memory to the APn register.
Data Memory Address Unit For some instructions, the 5-bit string processor can also preincrement or predecrement the AP pointer-value by +1 or –1, before being used by the accumulator register block. This utility can be effectively used to minimize software overhead in manipulating the accumulator address. The premodification of the address avoids the software pipelining effect that post-modification would cause.
Data Memory Address Unit Figure 2–6. Data Memory Address Unit Arithmetic Block RAM Address R0 R1 R2 R3 R4 R5 R6 R7 LOOP INDEX PAGE STACK Register Addressing Mode Internal Databus Internal Program Bus 2.3.1 RAM Configuration The data memory block (RAM) is physically organized into 17-bit parallel words. Within each word, the extra bit (bit 16) is used as a flag bit or tag for op-codes in the instruction set.
Data Memory Address Unit There are two-byte instructions, for example MOVB, which cause the processor to read or write data in a byte (8-bit) format. (The B appearing at the end of MOVB designates it as an instruction, which uses byte-addressable arguments.) The byte-addressable mode causes the hardware to read/write either the upper or lower 8 bits of the 16-bit word based on the LSB of the address. In this case, the address is a byte address, rather than a word address.
Program Counter Unit 2.4 Program Counter Unit The program counter unit provides addressing for program memory (onboard ROM). It includes a 16-bit arithmetic block for incrementing and loading addresses. It also consists of the program counter (PC), the data pointer (DP), a buffer register, a code protection write-only register, and a hardware loop counter (for strings and repeated-instruction loops). The program counter unit generates a ROM address as output.
Memory Organization: RAM and ROM 2.6 Memory Organization: RAM and ROM Data memory (RAM) and program memory (ROM) are each restricted to internal blocks on the C614. The program memory is read-only and limited to 32K, 17-bit words. The lower 2048 of these words is reserved for an internal test code and is not available to the user. The data memory is static RAM and is limited to 640, 17-bit words. 16 bits of the 17-bit RAM are used for the data value, while the extra bit is used as a status flag.
Memory Organization: RAM and ROM Figure 2–7.
Memory Organization: RAM and ROM When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend as far as width of location. Within a 16-bit accumulator, the desired bits (width of location) should be right-justified. The write operation is accomplished using the OUT instruction, with the address of the I/O port as an argument. A read from these locations is accomplished using the IN instruction, with the address of the I/O port as an argument.
Memory Organization: RAM and ROM Table 2–2.
Memory Organization: RAM and ROM 3.1.5, Internal and External Interrupts, for more information regarding the specific conditions for each interrupt-trigger event. The branch operation, however, is also contingent on whether the interrupt service has been enabled. This is done individually for each interrupt, using the interrupt mask bits within the interrupt/general control register. Refer to Section 2.7, Interrupt Logic, for more details.
Memory Organization: RAM and ROM The protection modes are implemented on the C614 as follows. Within the ROM is a dedicated storage for the block protection word (address 0x7FFE). The block protection word is divided into two 6-bit fields and two single-bit fields. The remainder of the 17-bit word is broken into three single-bit fields which are reserved for future use.
Memory Organization: RAM and ROM [(NTM + 1) * 512 – 1] = highest ROM address within the block to be protected (NTM + 1) * 512 = lowest ROM address which is left unprotected NTM = the value programmed at TM5…TM0 (true protection marker) ≡ the binary complement of NTM NFM NFM = the value programmed at FM5…FM0 (false protection marker) The purpose of the true and false protection markers is to provide parity. An erased P614 EPROM cell defaults to the value 1.
Interrupt Logic When the device is powered up, the hardware initialization circuit reads the value stored in the block protection word. The value is then loaded to an internal register and the security state of the ROM is identified. Until this occurs, execution of any instructions is suspended. The same initialization sequence is executed before entry into the special test-modes available on the P614 and C614 (EPROM mode, emulation mode, and trace mode).
Interrupt Logic the RESET low, assuming there is no interruption in power. For a full description of the interrupt-trigger events, refer to Section 3.1.5, Internal and External Interrupts.
Interrupt Logic Note: Setting a Bit in the IFR Using the OUT Instruction Setting a bit within the IFR using the OUT instruction is a valid way of obtaining a software interrupt. An IFR bit may also be cleared, using OUT, at any time. Assuming the global interrupt enable is set and the specific bit within the IMR is set, then, at the time of the interrupt-trigger event, an interrupt service branch is initiated. (The trigger event is marked by a 0-to-1 transition in the IFR bit).
Interrupt Logic Figure 2–8 provides an overview of the interrupt control sequence. INT0 is the highest priority interrupt, and INT7 is the lowest priority interrupt. Figure 2–8.
Timer Registers In addition to being individually enabled, all interrupts must be GLOBALLY enabled before any one can be serviced. Whenever interrupts are globally disabled, the interrupt flag register may still receive updates on pending trigger events. Those trigger events, however, are not serviced until the next INTE instruction is encountered. After an interrupt service branch, it is the responsibility of the programmer to re-SET the global interrupt enable, using the INTE instruction. 2.
Timer Registers (16-bit wide location) 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 P P P P P PRD1 register† address 0x3A P P P P TIMER1 Period P P P P P P P TIM1 register† address 0x3B T T T T T TIMER1 Count-Down T T T T T T PRD2 register address 0x3E P P P P TIMER2 Period P P P P P P P TIM2 register address 0x3F T T T T T TIMER2 Count-Down T T T T T T T T T T T Triggers INT1 on underflow P P P P P T T T T T Triggers INT2 on underflow P : per
Timer Registers Selection between the timer-source options is made using two control bits in the interrupt/general control register (IntGenCtrl). The IntGenCtrl is a 16-bit port-addressed register at 0x38. Clearing bit 8 selects 1/2 MC as the source for TIMER1. Setting bit 8 selects the reference oscillator as the source for TIMER1. Similarly, clearing bit 9 of the IntGenCtrl selects 1/2 MC as the source for TIMER2. Setting bit 9 selects the reference oscillator as the source for TIMER2.
Clock Control 2.9 Clock Control 2.9.1 Oscillator Options The C614 has two oscillator options available. Either option may be enabled using the appropriate control bits in the clock speed control register (ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3, Clock Speed Control Register. The first oscillator option, called the resistor-trimmed oscillator (RTO), is useful in low-cost applications where accuracy is less critical.
Clock Control The maximum required CPU clock frequency for the C614 is 8 MHz over the entire VDD range. This rate applies to the speed of the core processor. Higher CPU clock frequencies may be achieved, but these are not qualified over the complete range of supply voltages in the guaranteed specification. Figure 2–9.
Clock Control Note: ClkSpdCtrl Bits 8 and 9 When bit 8 is set in the ClkSpdCtrl register, the crystal oscillator bit (bit 9) becomes the least significant bit of the 6-bit resistor trim value. Thus, bits 15–11 and 9 make up the 6-bit resistor trim value. For example, if the ClkSpdCtrl register is 00010X11XXXXXXXX (X means don’t care, bold numbers are resistor trim bits), then the resistor trim value is equal to five.
Clock Control Bit 10 in the ClkSpdCtrl is idle state clock control. The level of deep-sleep generated by the IDLE instruction is partially controlled by this bit. When this bit is cleared (default setting), the CPU Clock is stopped during the sleep, but the MC remains running. When the idle state clock control bit is set, both the CPU clock and the MC are stopped during sleep. Refer to section 2.12 for more information regarding the C614’s reduced-power modes.
Execution Timing However, the general specification of the adjustment can be useful in certain circumstances. For example, the adjustment can be used to obtain a programmatic increase or decrease in the speed of the RTO reference. The default value for the adjustment, after RESET low, is all zeros. The zero value generates the slowest programmable rate for the RTO reference. The maximum value, 0x3F, generates the fastest programmable rate for the RTO reference.
Reduced Power Modes Figure 2–10. Instruction Execution and Timing CLOCK FETCH N N+1 N+2 N+3 N+4 N+5 N+6 DECODE N–1 N N+1 N+2 N+3 N+4 N+5 EXEC N–2 N–1 N N+1 N+2 N+3 N+4 DATA ADD PC ADD N N–1 N+1 N N+2 N+1 N+2 N+3 N+4 N+3 N+4 N+5 N+7 N+5 N+5 N+6 N+7 2.11 Reduced Power Modes The power consumption of the C614 is greatest when the DAC circuitry is called into operation, i.e., when the synthesizer speaks.
Reduced Power Modes The deepest sleep achievable on the C614, for example, is a mode where all of the previously listed subsytems are stopped. In this state, the device draws less than 10 µA of current and obtains the greatest power savings. It may be awakened from this state using an external interrupt (input port). A number of control parameters determine which of the internal components are left running after the IDLE instruction.
Reduced Power Modes The power consumed during sleep when the RTO oscillator is left running is greater than the power consumed during sleep when the CRO oscillator is left running. If the idle state clock control is clear, then the PLL circuitry, active during sleep, will attempt to regulate the MC to whatever frequency is programmed in the PLL multiplier (see Section 2.9.3, Clock Speed Control Register).
Reduced Power Modes Table 2–3. Programmable Bits Needed to Control Reduced Power Modes → deeper sleep … relatively less power → Label for Control Bit LIGHT MID DEEP Idle state clock control bit 10 ClkSpdCtrl register (0x3D) A 0 1 1 Enable reference oscillator bit 09 : CRO or bit 08 : RTO ClkSpdCtrl register (0x3D) B 1 1 0 ARM bit 14 IntGenCtrl register (0x38) C 0 1 1 Enable PDM pulsing bit 02 DAC Control register (0x34) D Should be cleared before any IDLE instruction.
Reduced Power Modes Table 2–4.
Reduced Power Modes The interrupt-trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER. In order for a TIMER underflow to occur during sleep, the TIMER must be left running before going to sleep. In certain cases, however, the act of going to sleep can bring a TIMER to stop, thereby preventing a TIMER-induced wake-up. The bottom row of Table 2–4 illustrates the various conditions under which the TIMER will continue to run after the IDLE instruction.
Reduced Power Modes In order to wake the device using a programmable interrupt, the interrupt mask register must have the respective bit set to enable interrupt service (see Section 2.7, Interrupt Logic). In some cases, the ARM bit must also be set, in order for the interrupts to be visible during sleep Table 2–3. After the C614 wakes from sleep, the program counter assumes a specific location, resuming normal operation of the device.
Chapter 3 Peripheral Functions This chapter describes in detail the MSP50C614 peripheral function, i.e., I/O control ports, general purpose I/O ports, interrupt control registers, comparator and digital-to-analog (DAC) control mechanisms. Topic Page 3.1 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 3.2 Digital-to-Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 3.3 Comparator . . .
I/O 3.1 I/O The C614 has 64 input-output pins. Forty of these are software configurable as either inputs or outputs. Eight are dedicated inputs, and the remaining sixteen are dedicated outputs. 3.1.1 General-Purpose I/O Ports The forty configurable input/output pins are organized in 5 ports, A,B,C,D, and E. Each port is one byte wide. The pins within these ports can be individually programmed as input or output, in any combination.
I/O is 0x00 (all inputs). The state of the data registers after RESET low is unknown (input state provided by external hardware). The 8-bit width is the true size of the mapped location. This is independent of the address spacing, which is greater than 8-bits. When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend across 8 bits. Within a 16-bit accumulator, the desired bits should be right-justified.
I/O 3.1.2 Dedicated Input Port F Port F is an 8-bit wide input-only port. The data presented to the input pin can be read by referring to the appropriate bit in the F port data register, address 0x28. This is done using the IN instruction, with the 0x28 address as an argument. The state of the F port data registers after RESET low is unknown (input state provided by external hardware) Each of the pins at port F has a programmable pull-up resistor. The resistance of these pullups is at least 100 kΩ.
I/O 3.1.3 Dedicated Output Port G Port G is a 16-bit wide output-only port. The output drivers have a Totem-Pole configuration. The data driven by the output pin can be controlled by setting or clearing the appropriate bit in the G port Data register, address 0x2C. This is done using the OUT instruction, with the 0x2C address as an argument. After RESET low, the default settings for the G port outputs are 0 (logical low).
I/O 3.1.4 Branch on D Port Instructions exist to branch conditionally depending upon the state of ports D0 and D1. These conditionals are COND1 and COND2, respectively. The conditionals are supported whether the D0 and D1 ports are configured as inputs or as outputs. The following table lists the four possible logical states for D0 and D1, along with the software instructions affected by them. D0 = 1 COND1 = TRUE. . . CIN1 CNIN1 JIN1 JNIN1 has its conditional call taken.
I/O Registers). INT1 and INT2 are high-priority, internal interrupts triggered by the underflow conditions on TIMER1 and TIMER2, respectively. Please refer to Section 2.8, Timer Registers, for a full description of the TIMER controls and their underflow conditions. When properly enabled, any of these interrupts may be used to wake the device up from a reduced-power state. In a deep-sleep state, they can also be used to wake the device when used in conjunction with the ARM bit. Please refer to Section 2.
Digital-to-Analog Converter (DAC) 3.2 Digital-to-Analog Converter (DAC) The C614 incorporates a two-pin pulse-density-modulated DAC which is capable of driving a 32 Ω loudspeaker directly. To drive loud speakers other than 32 Ω, an external impedance-matching circuit is required. 3.2.1 Pulse-Density Modulation Rate The rate of the master clock (MC) determines the pulse-density-modulation (PDM) rate, and this governs the output sampling-rate and the achievable DAC resolution.
Digital-to-Analog Converter (DAC) DAC Control register Address 0x34 (4-bit wide location) 03 02 01 00 Set DAC resolution to 8 bits: Set DAC resolution to 9 bits: Set DAC resolution to 10 bits: DM DM DM E E E 0 0 1 0 1 0 DM : Drive Mode selection (0 = C3x style : 1 = C5x style) E : pulse-density-modulation Enable (overall DAC enable) 0x0 : default state of register after RESET low Bit 2 in the DAC control register is used to enable/disable the pulse-density modulation.
Digital-to-Analog Converter (DAC) style. Their selection is made at bit 3 of the DAC control register (0x34). The C3x style is selected by clearing bit 3, and the C5x style is selected by setting bit 3. The default value of the selection is zero which yields the C3x style. The overflow bits appear in the DAC data register (14 and 13) to the left of the MSB data bit (12). In the C3x style mode, the overflow bits serve as a 2-bit buffer to handle overflow in the value field (bits 12…3).
Digital-to-Analog Converter (DAC) For a given sampling rate and DAC resolution, the CPU clock rate may be increased, if necessary, through the use of over-sampling. In the previous example, an original sampling rate of 8 kHz and a PDM rate of 4 MHz was used. A 2-times over-sampling, therefore, would require the PDM rate to be 8 MHz. This can be accomplished in two ways: PDM rate = 8 MHz : Set the master clock to 8 MHz also (ClkSpdCtrl). Set the PDMCD bit to 1: 1x master clock (IntGenCtrl).
Digital-to-Analog Converter (DAC) 8 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference DAC Precision IntGenCtrl PDMCD Bit OverSampling Factor ClkSpdCtrl PLLM Register Value (hex) 8 bits 1 1x 0x 0F 2.10 2.10 1.05 8.19 128 128 2x 0x 1E 4.06 4.06 2.03 15.87 128 256 4x 0x 3E 8.26 8.26 4.13 32.26 128 512 8x 0x 7C 16.38 16.38 8.19 64.00 128 1024 1x 0x 1E 4.06 2.03 2.03 7.94 256 256 2x 0x 3E 8.26 4.13 4.13 16.13 256 512 4x 0x 7C 16.38 8.19 8.
Digital-to-Analog Converter (DAC) 10 kHz Nominal Synthesis Rate 32.768 kHz Oscillator Reference DAC Precision IntGenCtrl PDMCD Bit OverSampling Factor ClkSpdCtrl PLLM Register Value (hex) 8 bits 1 1x 0x 13 0 9 bits 1 0 10 bits “1” “0” Master Clock Rate (MHz) 2.62 Number of Instructs Between DAC Interrupts Number of Instructs Between 10 kHz Interrupts 10.24 128 128 PDM RATE (MHZ) CPU Clock Rate (MHz) Output Sampling Rate (kHz) 2.62 1.31 2x 0x 26 5.11 5.11 2.56 19.
Comparator 3.3 Comparator The C614 provides a simple comparator that is enabled by a control register option. The inputs of the comparator are shared with pins PD4 and PD5. PD5 is the noninverting input to the comparator, and PD4 is the inverting input. When the comparator is enabled, the conditional operation COND2 (normally associated with PD1) becomes associated with the comparator result.
Comparator bit is automatically CLEARed again if an INT6 event occurs at the same time that the associated mask bit is SET (IntGenCtrl, address 0x38, bit 6). The latter indicates that the program vectoring associated with INT6 is enabled. (The flag bit is SET when the INT event occurs. Only if the mask bit is set, does the interrupt service occur: vectoring takes place and the flag bit is once again cleared. Refer to Section 2.
Comparator The comparator, along with all of its associated functions, is enabled by setting bit 15 of the interrupt/general control register (IntGenCtrl, address 0x38). The default value of the register is zero: comparator disabled. Note: IntGenCtrl Register Bit 15 At the time that bit 15 in the IntGenCtrl is set, PD4 and PD5 become the comparator inputs. At any time during which bit 15 is set, PD4 and PD5 MUST be set to INPUT (I/O Port D Control, address 0x1C, bits 4 and 5 CLEARed).
Interrupt/General Control Register 3.4 Interrupt/General Control Register The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The service branch enable status for each of the eight interrupts is registered in the IMR. A SET bit in the IMR enables that interrupt to assume the service branch (at the time that the associated trigger event occurs).
Interrupt/General Control Register The upper four bits in the IntGenCtrl have independent functions. Bit 12 is the enable bit for the pull-up resistors on input port F. Setting this bit engages all 8 F-port pins with at least 100-kΩ pull-ups (see Section 3.1.2, Dedicated Input Port F) Bit 13 is the PDMCD bit for the pulse-density modulation clock. Clearing this bit yields a PDM clock rate equal to one-half the frequency of the master clock (i.e., the CPU clock rate).
Hardware Initialization States 3.5 Hardware Initialization States The RESET pin is configured at all times as an external interrupt. It provides for a hardware initialization of the C614. When the RESET pin is held low, the device assumes a deep sleep state and various control registers are initialized. After the RESET pin is taken high once again, the Program Counter is loaded with the value stored in the RESET Interrupt Vector.
Hardware Initialization States Note: Internal RAM State after Reset The RESET low will not change the state of the internal RAM, assuming there is no interruption in power. This applies also to the interrupt flag register. The same applies to the states of the accumulators in the computational unit. When RESET is brought back high again, many of the programmable controls and registers are left in their default states: RESET high, just after low . . . - No reference oscillator is enabled.
Hardware Initialization States Note: Stack Pointer Initialization The software stack pointer (R7) must be initialized by the programmer, so that it points to some legitimate address in data memory (RAM). This must be done prior to any CALL or CCC instruction. If this is not done, then the first push/pop operation performed on the STACK will render the Program Counter to an unknown state. Table 3–2.
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Chapter 4 Assembly Language Instructions This chapter describes in detail about MSP50P614/MSP50C614 assembly language. Instruction classes, addressing modes, instruction encoding and explanation of each instruction is described. Topic Page 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 4.2 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 4.
Introduction 4.1 Introduction In this chapter each MSP50P614/MSP50C614 class of instructions is explained in detail with examples and restrictions. Most instructions can individually address bits, bytes, words or strings of words or bytes. Usable program memory is 30K by 17-bit wide and the entire 17-bits are used for instruction set encoding. The execution of programs can only be executed from internal program memory. Usable program memory starts from location 800h.
System Registers or by 2 for double word instructions) each execution cycle and points to the next program memory location to fetch. During a maskable interrupt, the next PC address is stored in the TOS register and is reloaded from TOS after the interrupt encounters an IRET instruction. Call and jump instructions also store the next instruction address by adding PC+2 and then storing the result in the TOS register. Upon encountering a RET instruction, the TOS value is reloaded to the PC.
System Registers It is recommended to avoid using the TOS register altogether in applications and leave its operation to development tools only. 4.2.6 Product High Register (PH) This register holds the upper 16 bits of the 32 bit result of a multiplication, multiply-accumulate, or shift operation. The lower 16 bits of the result are stored in the PL register. The PH register can be loaded directly by MOV instructions.
System Registers During accumulator read operations, both An and offset An~ are fetched. Depending on the instruction, either or both registers may be used. In addition, some write operations allow either register to be selected. The accumulator block can also be used in string operations. The selected accumulator (An or An~) is the least significant word (LSW) of the string and is restored at the end of the operation. String instructions are described in detail in section 4.8. 4.2.
System Registers value of the STACK register should be stored before use and restored after use. This register must point to the beginning of the stack in the RESET initialization routine before any CALL instruction or maskable interrupts can be used. CALL instructions increment R7 by 2., RET instructions decrement R7 by 2. The stack in MSP50P614/MSP50C614 is positively incremented. 4.2.11 String Register (STR) The string register (STR) holds the length of the string used by all string instructions.
System Registers Table 4–1. Status Register (STAT) Bit Name Function 0 XM Sign extended mode bit. This bit is one, if sign extension mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. 1 UM Unsigned multiplier mode. This bit is one if unsigned multiplier mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6. 2 OM Overflow mode. This bit is one if overflow (saturation) mode is enabled. See MSP50P614/MSP50C614 Computational Modes, Section 4.6.
Instruction Syntax and Addressing Modes 4.3 Instruction Syntax and Addressing Modes MSP50P614/MSP50C614 instructions can perform multiple operations per instruction. Many instructions may have multiple source arguments. They can premodify register values and can have only one destination. The addressing mode is part of the source and destination arguments.
Instruction Syntax and Addressing Modes 4.3.2 Addressing Modes The addressing modes on the MSP50P614/MSP50C614 are immediate, direct, indirect with post modification, and three relative modes. The relative modes are: - Relative to the INDEX or R5 register. The effective address is (indirect register + INDEX). Short relative to the PAGE or R6 register. The effective address is (PAGE+7 bit positive offset). Long relative to Rx. The effective address is (indirect register Rx + 16 bit positive offset).
Instruction Syntax and Addressing Modes Table 4–3. Rx Bit Description Rx Operation 0 0 0 R0 0 0 1 R1 0 1 0 R2 0 1 1 R3 1 0 0 R4 or LOOP 1 0 1 R5 or INDEX 1 1 0 R6 or PAGE 1 1 1 R7 or STACK Table 4–4.
Instruction Syntax and Addressing Modes Table 4–5. MSP50P614/MSP50C614 Addressing Modes Summary ADDRESSING SYNTAX OPERATION Direct name [dest,] [src,] *dma16 [*2] [, next A] name *dma16 [*2] [,src] [, next A] Second word operand (dma16) used directly as memory address. Long Relative name [dest] [,src] ,*Rx+offset16 [, next A] name *Rx+offset16 [,src] [, next A] Selects one of 8 address registers as base value and adds the value in the second word operand. Does not modify the base address register.
Instruction Syntax and Addressing Modes For any particular addressing mode, replace the {adrs} with the syntax shown in Table 4–4. To encode the instruction, replace the am, Rx and pm bits with the bits required by the addressing mode (Table 4–4).
Instruction Syntax and Addressing Modes 4.3.3 Immediate Addressing The address of the memory location is encoded in the instruction word or the word following the opcode is the immediate value. Single word instructions take one clock cycle and double word instructions take two clock cycles. Syntax: name dest, [src,] imm [, next A] Where: imm is the immediate value of a 16 bit number. Example 4.3.1 ADD AP0, 0x1A Assume the initial processor state in Table 4–8 before execution of this instruction.
Instruction Syntax and Addressing Modes 4.3.4 Direct Addressing Direct addressing always requires two instruction words. The second word operand is used directly as the memory address. The memory operand may be a label or an expression. Syntax: name [dest,] [src,] *dma16 [* 2] [, next A] name *dma16 [* 2] [, src] [, next A] Memory Operand Operand Note the multiplication by 2 with the data memory address. This only needs to be done for word addresses, i.e., the address that points to 16-bit words.
Instruction Syntax and Addressing Modes 4.3.5 Indirect Addressing Indirect addressing uses one of 8 registers (R0...R7) to point memory addresses. The selected register can be post-modified. Modifications include increments, decrements, or increments by the value in the index register (R5). For post-modifications, the register increments or decrements itself by 2 for word operands and by 1 for byte operands. Syntaxes are shown in Table 4–9. Table 4–9.
Instruction Syntax and Addressing Modes Example 4.3.12 MOV *R5++R5, A0~, ++A Refer to the initial processor state in Table 4–8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19. The contents of AC19 are stored in the data memory location in R5. R5 is then incremented by R5. Final result, AP0=3, R5 = 0x0004, *0x0002 = 0xFEED. Example 4.3.13 MOV A2, *R0 Refer to the initial processor state in Table 4–8 before execution of this instruction.
Instruction Syntax and Addressing Modes Address Rx (x = 0 – 7) + Index Register (R5) Operand Example 4.3.17 AND A0, *R3+R5 Refer to the initial processor state in Table 4–8 before execution of this instruction. A0 is accumulator AC2. The contents of the data memory byte location pointed to by R3+R5 is ANDed with AC2. The result is stored in AC2. The values in R3 and R5 are unchanged. Final result, AC2 = AC2 AND *0x01F2 = 0x13F0 AND 0x12AC = 0x12A0. Example 4.3.
Instruction Syntax and Addressing Modes Example 4.3.20 MOV A3, *R6+0x10 Refer to the initial processor state in Table 4–8 before execution of this instruction. Load A3 (AC29) with the contents of byte address, R6+0x10. The value of R6 is unchanged. Final result, AC29=0x0112. Example 4.3.21 ADD A0~, A0, *R6+0x10, ++A Refer to the initial processor state in Table 4–8 before execution of this instruction. Preincrement AP0. After preincrement, A0 is AC3 and A0~ is AC19.
Instruction Syntax and Addressing Modes 4.3.7 Flag Addressing This addressing mode addresses only the 17th bit (the flag/tag bit) located in data memory. This addressing applies to Class 8a instructions as explained in section 4.4. Using flag addressing, the flag bit can be loaded or saved. In addition, various logical operations can be performed without affecting the remaining 16 bits of the selected word. Two addressing modes are provided.
Instruction Syntax and Addressing Modes 4.3.8 Tag/Flag Bits The words TAG and flag may be used interchangeably in this manual. The TAG bit is the 17th bit of a word of data memory. There are 640 words of RAM, each 17 bits wide, on the C614. Therefore, there are 640 TAG bits on the C614. When an instruction of the format, MOV accumulator, RAM is performed, the STAT register is affected by various properties of this transfer.
Instruction Syntax and Addressing Modes However, xFLAG instructions use {flagadrs} addressing modes. This includes global (dma6) and relative (R6 + 6–bit offset). Both take only one clock cycle.
Instruction Classification 4.4 Instruction Classification The machine level instruction set is divided into a number of classes. The classes are primarily divided according to field references associated with memory, hardware registers, and control fields. The following descriptions give class-encode bit assignments, the OP code value within the class, and the abbreviated field descriptions.
Instruction Classification Table 4–11. Symbols and Explanation (Continued) Symbol Explanation next A Accumulator control bits as described in Table 4–6. [next A] The preincrement (++A) or predecrement (– –A) operation on accumulator pointers An or An~. Not NOT condition on conditional jumps, conditional calls or test flag instructions. nR Value in the repeat counter loaded by repeat instruction. ns Value in string register STR. offset[n] n bit offset from a reference register.
Instruction Classification Table 4–11.
Instruction Classification Table 4–12.
Instruction Classification Class 1a provides the four basic instructions of load, store, add, and subtract between accumulator and data memory. Either the accumulator or the offset accumulator (A~ bit dependent) can be stored in memory with the MOV instruction. The MOV instruction can load the accumulator (or its offset) depending on the ~A bit. The ADD or SUB instructions add or subtract memory from an accumulator register and save the results in the accumulator register (~A=0) or its offset (~A=1).
Instruction Classification Table 4–15. Class 1b Instruction Description C1b Mnemonic Description 0 0 0 0 OR An, {adrs} ORS An, {adrs} Logical OR the contents of the data memory location in {adrs} and the selected accumulator. Result(s) stored in accumulator(s). ALU status is modified 0 0 0 1 AND An, {adrs} ANDS An, {adrs} Logical AND the contents of the data memory location in {adrs} and the accumulator. Result(s) stored in accumulator(s).
Instruction Classification Table 4–15. Class 1b Instruction Description (Continued) C1b Mnemonic Description 1 0 1 1 MULAPL An, {adrs} MULAPLS An, {adrs} Multiply the MR register by the addressing mode {adrs} and add the lower 16 bits of the product to the accumulator. Latch the upper 16 bits into the PH register. ALU status is modified. 1 1 0 0 SHLTPL An, {adrs} SHLTPLS An, {adrs} Shift left n bits (SV reg).
Instruction Classification constants. Long constants (16 bits) and long string constants differ in that references are made to constants in the second word of the two-word instruction word. References made to a single 16 bit integer constant are immediate. That is, the actual constant value follows the first word opcode in memory.
Instruction Classification Table 4–18. Class 2b Instruction Description C2b Mnemonic Description 0 0 0 ADD An[~], An[~], imm16 [, next A] ADDS An[~], An[~], pma16 Add long constant to accumulator (or offset accumulator if A~=1) and store result to accumulator (~A=0) or offset accumulator (~A=1). ALU status modified. 0 0 1 MOV An[~], imm16 [, next A] MOVS An[~], pma16 Load long constant to accumulator (~A=0 or 1). ALU status is modified.
Instruction Classification between the accumulator and the MR, SV, or PH register. As with all accumulator referenced instructions, string operations are possible as well as premodification of one of 4 indirectly referenced accumulator pointer registers (AP). Table 4–19. Class 3 Instruction Encoding Bit 16 15 14 13 12 Class 3 1 1 1 0 0 11 10 9 next A 8 7 An 6 5 C3 4 3 2 1 0 0 A~ ~A Table 4–20.
Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 0 1 0 0 0 XOR An[~], An~, An [, next A] XORS An[~], An~, An Logically exclusive OR accumulator with offset accumulator and store the results in accumulator (~A=0 or 1). ALU status is modified. 0 1 0 0 1 OR An[~], An~, An [, next A] ORS An[~], An~, An Logically OR accumulator with offset accumulator and store results into accumulator (~A=0 or 1). ALU status is modified.
Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 0 1 0 0 MOV SV, An[~] [, next A] MOVS SV, An[~] Transfer accumulator(A~=0) or offset accumulator (A~=1) to SV register. Transfer status is modified. 1 0 1 0 1 MOV PH, An[~] [, next A] MOVS PH, An[~] Transfer accumulator (A~=0) or offset accumulator (A~=1) to PH register. Transfer status is modified.
Instruction Classification Table 4–20. Class 3 Instruction Description (Continued) C3 Mnemonic Description 1 1 1 1 0 MUL An[~] [, next A] MULS An[~] Multiply MR register by accumulator (A~=1) or offset accumulator (A~=0) and latch the rounded upper 16 bits of the resulting product into the PH register. 1 1 1 1 1 SHL An[~] [, next A] SHLS An[~] Barrel shift the accumulator (A~=1) or offset accumulator (A~=0) value n bits left (n stored in SV register).
Instruction Classification Table 4–22. Class 4a Instruction Description C4a Mnemonic Description 0 MOV {adrs}, Rx Store Rx register to data memory referred by addressing mode {adrs}. Modify transfer status. 1 MOV Rx, {adrs} Load Rx with the value in data memory referred by addressing mode {adrs}. Modify transfer status. Table 4–23. Class 4b Instruction Description C4b Mnemonic Description 0 0 ADDB Rx, imm8 Add 8 bit positive constant to Rx register. Modify RX status.
Instruction Classification 4.4.5 Class 5 Instructions: Memory Reference Class 5 instructions provide transfer to and from data memory and all registers except accumulators and Rx which are included in classes 1 and 4. The registers referenced for both read and write operations are the multiplier register (MR), the product high register (PH), the shift value register (SV), the status register (STAT), the top of stack (TOS), the string register (STR), and the four accumulator pointer registers AP0 to AP3.
Instruction Classification Table 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 0 1 0 1 1 MOV {adrs}, TOS Store the contents of the top of stack (TOS) register to the data memory location referred by addressing mode {adrs}. Transfer status is modified. 0 1 1 0 0 STAG {adrs} Store 1 to the 17th bit of data memory location referred by {adrs}. Set the tag bit. 0 1 1 0 1 RTAG {adrs} Store 0 to the 17th bit of data memory location referred by {adrs}. Clear the tag bit.
Instruction Classification Table 4–27. Class 5 Instruction Description (Continued) C5 Mnemonic Description 1 1 1 1 0 RPT {adrs}8 Load repeat counter with lower 8 bits of data memory location referred by addressing mode {adrs}. Interrupts are queued during execution. 1 1 1 1 1 MOV STAT, {adrs} Load status (STAT) register with effective data memory location referred by addressing mode {adrs} (17 bits with TAG). 4.4.
Instruction Classification Table 4–30. Class 6b Instruction Description C6b Mnemonic Description 0 IN An[~], port6 INS An[~], port6 Transfer the port’s 16 bit value to an accumulator. Port addresses 0–63 are valid. ALU status is modified. 1 OUT port6, An[~] OUTS port6, An[~] Transfer a 16 bit accumulator value to the addressed port. Port addresses 0–63 are valid. Transfer status is modified. 4.4.
Instruction Classification Table 4–31.
Instruction Classification Table 4–31.
Instruction Classification Table 4–33. Class 8a Instruction Description C8a Mnemonic Description 0 0 0 MOV TFn, {flagadrs} Load flag bit (17th bit) from data memory referred by flag addressing mode {flagadrs} to either TF1 or TF2 in status register. Load with inverted value if Not =1.
Instruction Classification Table 4–35. Class 9a Instruction Encoding Bit 16 15 14 13 12 11 10 9 8 7 6 Class 9a 1 1 1 0 1 0 0 An Class 9b 1 1 1 1 1 1 0 C9a Class 9c 1 1 1 1 1 0 1 APn Class 9d 1 1 1 1 1 1 1 1 0 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 C9a 5 4 3 2 Rx 0 1 0 1 1 imm8 0 C9c imm5 x C9d 0 0 0 0 1 0 0 0 n 1 1 1 1 1 Table 4–36.
Bit, Byte, Word and String Addressing Table 4–38. Class 9c Instruction Description C9c Mnemonic Description 0 MOV APn, imm6 Load the accumulator pointer (AP) with a five bit constant. 1 ADD APn, imm5 Add a five bit constant imm5 to the referenced accumulator pointer(AP). Table 4–39. Class 9d Instruction Description C9d Mnemonic 0 0 0 0 BEGLOOP Description Marks the beginning of loop. Queue interrupts and pushes the next PC value onto a temporary stack location.
Bit, Byte, Word and String Addressing is a string of bytes. The length of the byte string is stored in the string register (STR). To define the length of a string, the STR register should hold the length of the string minus 2. For example, if the length of a byte string is 10, then STR should be 8. A byte string address can be even or odd. Byte string data is fetched from the lower address (starting address) one byte at a time to consecutive addresses.
Bit, Byte, Word and String Addressing Flag address: The flag (or TAG) address uses linear addressing from 0 to the size of data memory in 17 bit wide words (0 to 639 for MSP50P614/ MSP50C614). Only the 17th bit is accessible. When a word memory location is read, the corresponding flag for that location is always loaded into the TAG bit of the status register (STAT). The flag address always corresponds to a 17 bit wide word address.
Bit, Byte, Word and String Addressing Figure 4–4. Data Memory Example Absolute Word Memory Location Data Memory Location (even) = 2 * (Absolute word memory location) MS Byte LS Byte Data Memory Location (odd) 0x0000 0x0000 0x12 0x34 0x0001 0x0001 0x0002 0x56 0x78 0x0003 0x0002 0x0004 0x9a 0xbc 0x0005 0x0003 0x0006 0xde 0xf0 0x0007 0x0004 0x0008 0x11 0x22 0x0009 0x0005 0x000a 0x33 0x44 0x000b Example 4.5.
Bit, Byte, Word and String Addressing Example 4.5.7 MOV STR, 4–2 MOV AP0, 2 MOV R0, 0x0001 * 2 MOVBS A0, *R0++ Refer to Figure 4–4 for this example. The word-string length is 4. AP0 points to AC2 accumulator. R0 is loaded with 0x0002. The fourth instruction loads the value of the word-string at the RAM address in R0, 0x0002. R0 autoincrements by 2 after each fetch and stores them into four consecutive accumulators starting from AC2. The result is, AC2 = 0x5678, AC3 = 0x9ABC, AC4 = 0xDEF0, AC5 = 0x1122.
MSP50P614/MSP50C614 Computational Modes Example 4.5.10 MOV STR, 0 SFLAG *0x00032 MOVS A0, *0x0031 * 2 RFLAG *0x00032 MOVS A0, *0x0031 * 2 Refer to Figure 4–4 for this example. This example is to illustrate the effect of the tag/flag bit when used with a string instruction. The string register (STR) is loaded with 0 (string length of 2). The second instruction sets the flag bit to 1 at flag address 0x0032.
MSP50P614/MSP50C614 Computational Modes Table 4–41. MSP50P614/MSP50C614 Computational Modes Computational Mode Setting Instruction Resetting Instruction Function Sign extension SXM RXM STAT.XM = 1 produces sign extension on data as it is passed into accumulators. This mode copies the 16th bit of the data in the multiplier/multiplicand to the 17th bit. This causes signed multiplication of two signed numbers. STAT.XM = 0 suppresses sign extension. Unsigned none none STAT.
MSP50P614/MSP50C614 Computational Modes Example 4.6.2 SXM MOV STR, 2–2 ; string length=2 MOV MR, 0x8000 MOV A0, 0x8000, ++A ; load MS Byte MOV A0, 0x0000, ––A ; load LS Byte MULTPLS A0, A0 This example illustrates the sign extension mode on a string during multiplication. Here, two negative numbers 0x80000000 and 0x8000 are multiplied to obtain a positive number 0x400000000000. If the signs were not extended, we would have obtained 0xC00000000000, a negative number.
MSP50P614/MSP50C614 Computational Modes Example 4.6.1 SOVM MOV A0, 0x7FFE ADD A0, 5 In this example, we set the overflow mode (OM = 1 of STAT). Adding 0x7FFE with 5 causes an overflow (OF = 1 of STAT). Since the expected result is a positive value, the accumulator saturates to the largest representable value, 0x7FFF. If overflow mode was not set before the ADD instruction, then the accumulator would overflow. Therefore, the result, 0x8003, would be a negative value. Example 4.6.
Hardware Loop Instructions high word of the result is stored in the PH register and is 0x3FFF. The low word is stored in A0~ as 0x0001. If the two numbers are considered as Q15 fractional numbers (all bits are to the right of the decimal point), then the result will be a Q30 number. To translate a Q30 number back to a Q15 number, first left shift the number (MOV A0,PH, SHL A0,A0), and then truncate the lower word (ignore A0~). When fractional mode is set, the left shift is done automatically (MOV A0,PH).
Hardware Loop Instructions the execution of a string instruction, interrupts are queued. Queued interrupts are serviced according to their priority after the string operation is complete. In addition to repeat and string instructions, the combination of repeated string instructions has a very useful function. Since there is only one counter to control the hardware repeat count, it is not possible to nest repeats and strings.
String Instructions 4.8 String Instructions Class 1, 2, 3, and 6 instructions can have string modes. During the execution of string instruction, STR register value plus 2 is assumed as string length. An accumulator string is a group of consecutive accumulators spanning from An to the next N consecutive accumulators (N is the length of the string). The STR register should be loaded with N–2 to define a string length, N.
String Instructions A1 string is 0x233EFBCA1223 and *0x200 = 0x9086EE3412AC. STR = 3–2=1, defines a string length of 3. Final result, A1~ string = 0x233EFBCA1223 + 0x9086EE3412AC = 0xB3C5E9FE24CF, AC5=0x24CF, AC6=0xE9FE, AC7=0xB3C5, STR=2 (unchanged). Notice that this instruction has accumulated a carry. Special String Sequences: There are two string instructions that have a special meaning.
Lookup Instructions 4.9 Lookup Instructions Table lookup instructions transfer data from program memory (ROM) to data memory or accumulators. These instructions are useful for reading permanent ROM data into the user program for manipulation. For example, lookup tables can store initial filter coefficients, characters for an LCD display which can be read for display in the LCD screen, etc. There are four lookup instructions as shown in Table 4–44.
Lookup Instructions Lookup instructions make use of the data pointer (DP) internally. The DP stores the address of the program memory location, loads the value to the destination, and increments it automatically after every load. Thus, the value of the DP is always the last used program memory address plus one. The content of DP changes after the execution of lookup instructions. If filter instructions FIRK and CORK are used, it is required to context save DP in the interrupt service routine.
Input/Output Instructions 4.10 Input/Output Instructions The MSP50P614/MSP50C614 processor communicates with other on-chip logic as well as external hardware through a parallel I/O interface. Up to 40 I/O ports are addressable with instructions that provide bidirectional data transfer between the I/O ports and the accumulators. Data input is performed with the IN instruction (Class 6). This instruction uses a memory address and a 4-bit port address.
Special Filter Instructions N tap filters ideally require 2N multiply–accumulates. Four instructions are provided to compute this equation: FIR, FIRK, COR and CORK. All filter instructions require overflow modes to be reset since these instructions have built in overflow hardware. In addition, these instructions must be used with a RPT instruction. FIR and FIRK instructions perform 16-x-16 bit multiplies and 32-bit accumulation in 2 clock cycles (per tap).
Special Filter Instructions theory requires). The second to last RAM location in the circular buffer is tagged using an STAG instruction. Below is an example of how to set up circular buffering with FIR or COR. When using the FIR or COR instruction with circular buffering, RAM needs to be allocated for the circular buffer and the filter coefficients.
Special Filter Instructions After the FIR or COR instruction executes, the new startOfBuff will be the last location in the circular buffer. After another FIR/COR instruction, the new startOfBuff will be the second to last location in the circular buffer, and so on. The second detail is the STAT register. The STAT register must be saved immediately after every FIR or COR instruction. Consequently, this saved value must be loaded before every FIR or COR instruction.
Special Filter Instructions mov mov mov A0,*nextSample ;Replace last sample with newest sample *R0,A0 ; and update the start of the *startOfBuff,R0 ; circular buffer to here (R0) First, the overflow mode must be reset. Next, R5 must be loaded with the wrap around value of the circular buffer. Wrap around happens automatically. This tells the processor how many words to step back when the end of the circular buffer is reached.
Special Filter Instructions Any combination of registers different from the above will yield incorrect results with the FIR/COR instruction. tag 0x0106 0x010 x[k–3] x[k–2] x[k] x[k–1] Use R5 to wrap around R0 0x0100 0x0102 After FIR/COR execution The STAT register is saved in the filterSTAT_tag location. The output of the filtering operation in the example is located in AC0 (lower word) and AC1 (high word). This 32 bit result is stored in the SampleOut RAM location.
Special Filter Instructions Important note about setting the STAT register It is very important to consider the initial value of the filterSTAT_tag variable. Failure to set up the filterSTAT_tag variable can cause incorrect results in FIR/ COR operations. Overflow mode must always be reset. The overflow bit of the STAT register may not be set. For samples or filter coefficients that are signed, the sign extension mode bit must also be set.
Special Filter Instructions mov STAT,*filterSTAT_tag rpt firk mov N–2 A0,*R0++ ;Do one sample ––> 32 bit result *filterSTAT_tag,STAT ;save STAT with last filter tag status ;R0 now points to the last sample *ySampleOut,A0 ;FIR outputs bits 0–15 in AC0, 16–32 in AC1 movs mov A0,*nextSample mov mov *R0,A0 *startOfBuff,R0 ;load STAT with last filter tag status ;Replace last sample with newest sample and update ; the start of the ; circular buffer to here (R0) The set up for the FIRK/CORK instruction
Special Filter Instructions Figure 4–6.
Special Filter Instructions Figure 4–7.
Conditionals 4.12 Conditionals The condition bits in the status register (STAT) are used to modify program control through conditional branches and calls. Various combinations of bits are available to provide a rich set of conditional operations. These condition bits can also be used in Boolean operations to set the test flags TF1 and TF2 in the status register.
Legend 4.13 Legend All instructions of the MSP50P614/MSP50C614 use the following syntax: name [dest] [, src] [, src1] [, mod] name Name of the instruction. Instruction names are shown in bold letter through out the text. dest Destination of the data to be stored after the execution of the instruction. Optional for some instructions or not used. Destination is also used as both source and destination for some instructions. src Source of the first data. Optional for some instructions or not used.
Legend Symbol Meaning A~ Select offset accumulator as the source if this bit is 1. Used in opcode encoding only. ~A Select offset accumulator as the destination accumulator if this bit is 1. Used in opcode encoding only. A~ Select offset accumulator as the source if this bit is 0. Used in opcode encoding only. ~A~ Can be either ~A or A~ based on opcode (or instruction). Used in Opcode encoding only. An[~] Can be either An or An~ where n = 0...3 APn Accumulator Pointer register where n = 0..3.
Legend Symbol Meaning nR Value in repeat counter loaded by RPT instructions ns Value in string register STR OF Overflow flag offset[n] n bit offset from a reference register. OM Overflow mode PC Program counter, 16 bits pma[n] n bit program memory address. For example, pma8 means 8-bit program memory address. If n is not specified, defaults to pma16. port[n] n bit I/O port address. Certain instructions multiply this port address by 4.
Legend Table 4–45. Auto Increment and Decrement next A Operation No modification b9 b8 0 0 Auto increment ++A 0 1 Auto Decrement – –A 1 0 Table 4–46.
Individual Instruction Descriptions 4.14 Individual Instruction Descriptions In this section, individual instructions are discussed in detail. Use the conditionals in Section 4.12 and the legend in Section 4.13 to help with individual instruction descriptions.
Individual Instruction Descriptions 4.14.1 ADD Add word Syntax [label] name dest, src [, src1] [,mod] Clock, clk Words, w With RPT, clk ADD An[~], An, {adrs} [, next A] Table 4–46 Table 4–46 Table 4–46 1a ADD An[~], An[~], imm16 [, next A] 2 2 N/R 2b ADD An[~], An[~], PH [, next A] 1 1 nR+3 3 ADD An[~], An~, An [, next A] 1 1 nR+3 3 ADD Rx, imm16 2 2 N/R 4c ADD Rx, R5 1 1 nR+3 4d ADD† APn, imm5 1 1 N/R 9c Class † Does not affect the status flags.
Individual Instruction Descriptions Description Syntax Description ADD dest, src ADD src with dest and store the result to dest. ADD dest, src, src1 [,mod] ADD src1 with src and store the result to dest. Premodify the mod before execution. (if provided) See Also ADDB, ADDS, SUB, SUBB, SUBS Example 4.14.1.1 ADD A2, A2~, *R2++R5, ––A Decrement accumulator pointer AP2. Add word at address in R2 to A2~, put result in A2. Add value in R5 to R2 and store in R2. Example 4.14.1.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Example 4.14.3.3 ADDS A1, A1~, A1 Add accumulator string A1 to accumulator string A1~, put result in accumulator string A1. Example 4.14.3.4 MULAPL A0, A0~ ADDS A0, A0~, PH The first instruction multiplies MR and A0~, adds PL to A0, and stores the result in A0. The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0. Note that MULAPL and ADDS constitute a special sequence.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions See Also ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS Example 4.14.4.1 AND A3, *R4— – And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after the AND operation. Example 4.14.4.2 AND A0~, A0, 0xff0f, – –A Predecrement accumulator pointer AP0. And immediate value 0xff0f to register accumulator A0, store result in accumulator A0~. Example 4.14.4.3 AND TF2, *0x0020 AND global flag bit at RAM word location 0x0020 to TF2 in the STAT.
Individual Instruction Descriptions 4.14.5 ANDB Bitwise AND Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ANDB An, imm8 1 1 N/R 2a Execution dest ⇐ dest AND src byte PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 ANDB An, imm8 1 0 1 0 1 0 1 9 8 7 6 An 5 4 3 2 1 0 imm8 Description Bitwise AND src byte and byte stored in dest register and store result in dest register.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.7 BEGLOOP Begin Loop Syntax [label] name Clock, clk Word, w With RPT, clk Class 1 1 N/R 9d BEGLOOP† † Loop must end with ENDLOOP.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.9 Ccc Conditional Subroutine Call Syntax [label] name address Ccc† pma16 Clock, clk Word, w With RPT, clk Class 2 2 N/R 7c † Cannot immediately follow a CALL instruction with a return instruction.
Individual Instruction Descriptions Table 4–48.
Individual Instruction Descriptions Description If cc condition in Table 4–48 is true, PC + 2 is pushed onto the stack and the second word operand is loaded into the PC. If the condition is false, execution defaults to a NOP. A Ccc instruction cannot be followed by a return (RET) instruction. No restriction applies if IRET is used instead of RET.
Individual Instruction Descriptions Syntax Alternate Syntax Description CRC pma16 Conditional call on RCF = 1 CRNC pma16 Conditional call on RCF = 0 CRE pma16 CRZ pma16 Conditional call on RZF = 1 (equal)† CRNE pma16 CRNZ pma16 Conditional call on RZF = 0 (not equal)† CXG pma16 CXNLE pma16 Conditional call on transfer greater (signed)† CXNG pma16 CXLE pma16 Conditional call on transfer not greater (signed)† CXS pma16 Conditional call on XSF = 1 CXNS pma16 Conditional call on XSF = 0
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Example 4.14.10.3 CMP R2, 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly. Example 4.14.10.4 CMP R0, R5 Compare value at R0 to R5 and change the STAT flags accordingly.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.15 ENDLOOP End Loop Syntax [label] name # Clock, clk Word, w With RPT, clk Class ENDLOOP [n] 1 1 N/R 9d Execution If (R4 ≥ 0) decrement R4 by n (1 or 2) PC ⇐ first address after BEGLOOP else NOP PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 n Description This instruction marks the end of a loop defined by BEGLOOP.
Individual Instruction Descriptions 4.14.16 EXTSGN Sign Extend Word Syntax [label] name EXTSGN dest [, mod] Clock, clk Word, w With RPT, clk Class 1 1 nR+3 3 An[~] [, next A] Execution [premodify AP if mod specified] new most significant word of dest ⇐ STAT.
Individual Instruction Descriptions 4.14.17 EXTSGNS Sign Extend String Syntax [label] name EXTSGNS dest Clock, clk Word, w With RPT, clk Class nR+3 1 nR+3 3 An[~] Execution new most significant word of dest ⇐ STAT.SF PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 EXTSGNS An[~] 1 1 1 0 0 1 1 Description 9 8 An 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 A~ Extend the sign bit (SF) of most significant word an additional 16 bits to the left.
Individual Instruction Descriptions MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY EXTSGN A1 ; not string version as above Alternatively, the following code can do the same thing but requires more code: MOV AP0, 0 ; POINT TO LSW OF ACCUM STRING MOV AP1, 3 ; Point to loc corresponding to ; extended word in acc ZAC A1 ; INITIALIZE EXTENDED SIGN VALUE as positive MOVS A0, *R0 ; R0 POINTS TO VALUE IN MEMORY JNS POSITIVE ; branch around
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions See Also RPT, FIRK, COR, CORK Example 4.14.18.1 RPT 0 FIR A0, *R0 Computes the calculation for 2 tap FIR filter with 32-bit accumulation. See section 4.11 for more detail on the setup of coefficients and sample data.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.20 IDLE Halt Processor Syntax [label] name Clock, clk Word, w With RPT, clk Class IDLE 1 1 N/R 9d Execution Stop processor clocks PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDLE 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 Description Halts execution of processor. An external interrupt wakes the processor.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.22 INS Input From Port Into String Syntax [label] name INS src, src1 Clock, clk Word, w With RPT, clk Class nS+2 1 nR+2 6b An[~], port6 Execution dest ⇐ content of port6 PC ⇐ PC + 1 Flags Affected dest is An: OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 INS An[~], port6 1 1 1 0 1 1 1 9 8 An 7 6 5 4 3 port6 2 1 0 0 ~A Description Input string from same port, port6, to accumulator string.
Individual Instruction Descriptions 4.14.23 INTD Interrupt Disable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTD 1 1 N/R 9d Execution STAT.IM ⇐ 0 PC ⇐ PC + 1 Flags Affected None (IM is STAT bit 4) Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTD 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 Description Disables interrupts. Resets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 0. See Also INTE, IRET Example 4.
Individual Instruction Descriptions 4.14.24 INTE Interrupt Enable Syntax [label] name Clock, clk Word, w With RPT, clk Class INTE 1 1 N/R 9d Execution STAT.IM ⇐ 1 PC ⇐ PC + 1 Flags Affected None (IM is STAT bit 4) Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTE 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 Description Enables interrupts. Sets bit 4 (the IM, interrupt mask bit) of status register (STAT) to 1. See Also INTD, IRET Example 4.
Individual Instruction Descriptions 4.14.25 IRET Return From Interrupt Syntax [label] name Clock, clk Word, w With RPT, clk Class IRET 2 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 See Also RET, CALL, Ccc, INTE, INTD Description Return from interrupt. Pop top of stack to program counter. Example 4.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Opcode Instructions 16 15 14 13 12 11 10 Jcc pma16 1 0 0 0 0 0 Not 1 0 0 0 0 0 Not 1 0 0 0 0 0 Not 1 0 0 0 0 0 Not cc names cc name 5 4 3 2 1 0 0 0 0 0 0 Rx 0 1 Rx 1 0 Rx 1 1 cc cc cc pma16 x cc 6 pma16 x Jcc pma16, Rx++R5 7 cc pma16 x Jcc pma16, Rx–– 8 pma16 x Jcc pma16, Rx++ 9 Description True condition (Not true condition) Not cc name 0 0 0 0 0 Z NZ Conditional on ZF=1 (Not condition ZF=0
Individual Instruction Descriptions cc names cc cc name Description True condition (Not true condition) Not cc name 1 1 1 0 0 reserved 1 1 1 0 1 reserved 1 1 1 1 0 reserved 1 1 1 1 1 reserved Description PC is replaced with second word operand if condition is true (or unconditional). If test condition is false, a NOP is executed.
Individual Instruction Descriptions Syntax Alternate Instruction Description JRNLZP pma16 [, Rmod] Conditional jump on Rx ≥ 0 after post-mod JRZP pma16 [, Rmod] Conditional jump on Rx = 0 after post-mod JRNZP pma16 [, Rmod] Conditional jump on Rx ≠ 0 after post-mod JS pma16 [, Rmod] Conditional jump on SF = 1 JNS pma16 [, Rmod] Conditional jump on SF = 0 JTAG pma16 [, Rmod] Conditional jump on TAG = 1 JNTAG pma16 [, Rmod] Conditional jump on TAG = 0 JTF1 pma16 [, Rmod] Conditional jump on
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions [label] name dest, src, [, next A] Clock, clk Word, w With RPT, clk Class MOV TFn, {cc} [, Rx] 1 1 N/R 8b MOV STR, imm8 1 1 N/R 9b MOV SV, imm4 1 1 N/R 9b MOV APn, imm5 1 1 N/R 9c Execution [premodify AP if mod specified] dest ⇐ src PC ⇐ PC + w Flags Affected dest is An: dest is Rx: dest is {adrs}: src is {adrs} src is {flagadrs} OF, SF, ZF, CF are set accordingly RCF, RZF are set accordingly XSF, XZF are set accordingly TAG bit is set a
Individual Instruction Descriptions Instructions 16 15 14 13 12 11 10 9 8 7 6 5 MOV Rx, R5 1 1 1 1 1 1 1 0 0 1 1 0 MOV SV, imm4 1 1 1 1 1 1 0 1 0 0 0 0 MOV SV, {adrs}4 1 1 0 1 1 0 0 0 0 1 1 0 1 MOV APn, {adrs} 1 1 0 1 0 1 0 1 MOV {adrs}, PH 1 1 0 1 0 1 0 1 1 0 1 MOV {adrs}, DP 1 1 0 1 0 1 0 1 MOV {adrs}, TOS 1 1 0 1 0 1 1 1 0 0 1 0 1 1 0 1 APn adrs 1 1 1 1 1 adrs 1 1 1 0 0 1 adrs 0 1 0 0 0
Individual Instruction Descriptions Description Copy value of src to dest. Premodification of accumulator pointers is allowed with some operand types.
Individual Instruction Descriptions Syntax Description MOV STR, imm8 Move immediate byte to String Register (STR) MOV APn, imm5 Move immediate 5-bit value to APn register † Accumulator condition flags are modified to reflect the value loaded into either An or An~. ‡ Signed multiplier mode resets UM (bit 1 in status register) to 0 ¶ Load the logic value of the test condition to the TFn bit in the status register (STAT). If the condition is true, TFn=1, else TFn=0.
Individual Instruction Descriptions Example 4.14.28.13 MOV R1, 0x0200 * 2 Load immediate word memory address 0x0200 to R1. Example 4.14.28.14 MOV R7, (0x0280 – 32) * 2 Load R7 (stack register) with the starting value of stack, i.e., 0x0260. Example 4.14.28.15 MOV *0x0200 * 2, R0 Store R0 to data memory word location 0x0200. Example 4.14.28.16 Transfer R5 to R0. MOV R0, R5 Example 4.14.28.17 MOV AP2, *R3 Copy content of data memory location stored in R3 to accumulator pointer AP2. Example 4.14.28.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Example 4.14.29.2 MOVB *R2, A0 Copy lower 8 bits of accumulator A0 to the data memory byte pointed by R2. Example 4.14.29.3 MOVB A0, 0xf2 Load accumulator A0 with value of 0xf2. Example 4.14.29.4 MOVB MR, 34 Load MR register with immidiate value of 34 (decimal). Example 4.14.29.5 MOVB R2, 255 Load R2 with immidiate value of 255 (decimal).
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Description Copy value of src string to dest string. Premodification of accumulator pointers is allowed with some operand types.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.36 MOVT Move Tag From Source to Destination Syntax [label] name dest, src Clock, clk MOVT {adrs}, TFn Execution dest ⇐ src PC ⇐ PC + w Flags Affected None Word, w Table 4–46 With RPT, clk Class Table 4–46 5 Opcode Instructions 16 15 14 13 12 11 10 9 8 MOVT {adrs}, TFn 1 1 0 1 0 1 1 1 fig x 7 6 5 4 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Figure 4–8. Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set B MR/SV I/O xxxxxx PH xxxx00 S B Immediate B An B Rx S S B ROM B RAM APn STR S Flag Bit STAT TOS NOTE: B = Byte move possible. S = String move possible.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.39 MULS Multiply String With No Data Transfer Syntax [label] name src MULS An [~] Execution PH,PL ⇐ MR * src string PC ⇐ PC + 1 Flags Affected None Clock, clk Word, w With RPT, clk Class nS+3 1 nR+3 3 Opcode Instructions 16 15 14 13 12 11 10 MULS An[~] 1 1 1 0 0 1 1 9 8 An 7 6 5 4 3 2 1 0 1 1 1 1 0 0 A~ 0 Description Multiply MR and the value in src.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.48 NOP No Operation Syntax [label] name Clock, clk Word, w With RPT, clk Class NOP 1 1 nR+3 9d Execution PC ⇐ PC + 1 Flags Affected None (No operation) Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description This instruction performs no operation. It consumes 1 clock of execution time and 1 word of program memory. See Also RPT Example 4.14.48.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions See Also ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NOTACS Example 4.14.51.1 OR A0, *R0++R5 OR accumulator A0 with the value in data memory address stored in R0 and store result in accumulator A0, Add R5 to R0 after execution. Example 4.14.51.2 OR A1, A1, 0xF0FF, ++A Preincrement pointer AP1. OR immediate 0xF0FF to accumulator A1. Store result in accumulator A1. Example 4.14.51.3 OR A1, A1~, A1, ––A Pre–decrement accumulator pointer AP1.
Individual Instruction Descriptions 4.14.52 ORB Bitwise OR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class ORB An, imm8 1 1 N/R 2a Execution dest ⇐ dest OR src PC ⇐ PC + 1 Flags Affected OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 ORB An, imm8 1 0 1 0 1 0 0 9 8 An 7 6 5 4 3 2 1 0 imm8 Description Bitwise OR byte of src and dest. Result is stored in dest. Only lower 8 bits of accumulator is affected.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.55 OUTS Output String to Port Syntax [label] name dest, src OUTS port6, An[~] Execution port6 ⇐ src PC ⇐ PC + 1 Flags Affected XSF, XZF are set accordingly Clock, clk Word, w With RPT, clk Class nR+2 1 nR+2 6b Opcode Instructions 16 15 14 13 12 11 10 OUTS port6, An[~] 1 1 1 0 1 1 1 9 8 An 7 6 5 4 port6 3 2 1 0 1 ~A Description Output to I/O port.
Individual Instruction Descriptions Return From Subroutine (CALL, Ccc) 4.14.56 RET Syntax [label] name Clock, clk Word, w With RPT, clk Class RET 1 1 N/R 5 Execution PC ⇐ TOS R7 ⇐ R7 – 2 TOS ⇐ *R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RET 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 Description Return from call or vectored call. Pop stack to program counter, continue execution.
Individual Instruction Descriptions 4.14.57 RFLAG Reset Memory Flag Syntax [label] name src Clock, clk Word, w With RPT, clk Class 1 1 N/R 8a {flagadrs} RFLAG Execution memory flag bit at {flagadrs} data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 RFLAG {flagadrs} 1 0 0 1 0 0 0 0 1 1 6 5 4 3 2 1 0 flagadrs Description Reset flag at addressed memory location to 0.
Individual Instruction Descriptions 4.14.58 RFM Reset Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RFM 1 1 N/R 9d Execution STAT.FM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets fractional mode. Clears bit 3 in status register (STAT). Disable multiplier shift mode for unsigned fractional or integer arithmetic.
Individual Instruction Descriptions 4.14.59 ROVM Reset Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class ROVM 1 1 N/R 9d Execution STAT.OM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets overflow mode in status register bit 2 (the OM bit). Disable ALU saturation output (normal mode). See Also SOVM Example 4.14.59.
Individual Instruction Descriptions 4.14.60 RPT Repeat Next Instruction Syntax [label] name src Clock, clk RPT {adrs}8 RPT imm8 Word, w With RPT, clk Class N/R 5 N/R 9b Table 4–46 1 1 Execution IF RPT {adrs}8 load src to repeat counter. ELSE load imm8 to repeat counter. (mask interrupt) repeat next instruction (repeat counter value + 2) times.
Individual Instruction Descriptions 4.14.61 RTAG Reset Tag Syntax [label] name dest RTAG {adrs} Clock, clk Word, w Table 4–46 Execution memory tag bit at {adrs} data memory location ⇐ 0 PC ⇐ PC + 1 Flags Affected None With RPT, clk Class Table 4–46 5 Opcode Instructions 16 15 14 13 12 11 10 9 8 RTAG {adrs} 1 1 0 1 0 1 1 0 1 x 7 6 5 4 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
Individual Instruction Descriptions 4.14.62 RXM Reset Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class RXM 1 1 N/R 9d Execution STAT.XM ⇐ 0 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 Description Reset extended sign mode status register bit 0 (the XM bit) to 0. See Also SXM Example 4.14.62.
Individual Instruction Descriptions 4.14.63 SFLAG Set Memory Flag Syntax [label] name dest Clock, clk Word, w With RPT, clk Class 1 1 N/R 8a {flagadrs} SFLAG Execution memory flag bit at {flagadrs} data memory location ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 SFLAG {flagadrs} 1 0 0 1 1 1 0 1 0 1 6 5 4 3 2 1 0 flagadrs Description Set flag at addressed memory location.
Individual Instruction Descriptions 4.14.64 SFM Set Fractional Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SFM 1 1 N/R 9d Execution STAT.FM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Description Sets bit 3 (the FM bit) in status register (STAT) to 1. Enable multiplier shift mode for signed fractional arithmetic. Example 4.14.64.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.77 SOVM Set Overflow Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SOVM 1 1 N/R 9d Execution STAT.OM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOVM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Sets overflow mode in status register (STAT) bit 2 to 1. Enable ALU saturation output (DSP mode). See Also ROVM Example 4.14.77.
Individual Instruction Descriptions 4.14.78 STAG Set Tag Syntax [label] name dest STAG {adrs} Clock, clk Word, w Table 4–46 Execution memory tag bit at address adrs ⇐ 1 PC ⇐ PC + w Flags Affected None With RPT, clk Class Table 4–46 5 Opcode Instructions 16 15 14 13 12 11 10 9 8 STAG {adrs} 1 1 0 1 0 1 1 0 0 x 7 6 5 4 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] Description Sets the tag bit at the addressed memory location.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Syntax Description SUB An[~], An, {adrs} [, next A] Subtract effective data memory word from An[~], store result in An SUB An[~], An[~], imm16 [, next A] Subtract immediate word from An[~], store result in An[~] SUB An[~], An[~], PH [, next A] Subtract Product High (PH) register from An[~], store result in An[~] SUB An[~], An, An~ [, next A] Subtract An~ word from An word, store result in An[~] SUB An[~], An~, An [, next A] Subtract An word from An~ word, stor
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions Syntax Description SUBS An[~], An, {adrs} Subtract data memory string from An string, store result in An[~] string SUBS An[~], An[~], pma16 Subtract program memory string from An[~] string, store result in An[~] string SUBS An[~], An, An~ Subtract An~ string from An string, store result in An[~] string SUBS An[~], An~, An Subtract An string from An~ string, store result in An[~] string SUBS An[~], An[~], PH Subtract product high (PH) register from An[~] string
Individual Instruction Descriptions 4.14.82 SXM Set Extended Sign Mode Syntax [label] name Clock, clk Word, w With RPT, clk Class SXM 1 1 N/R 9d Execution STAT.XM ⇐ 1 PC ⇐ PC + 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SXM 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 Description Sets extended sign mode status register (STAT) bit 0 to 1. See Also RXM Example 4.14.82.1 SXM Set XM bit of STAT to 1.
Individual Instruction Descriptions 4.14.83 VCALL Vectored Call Syntax [label] name dest Clock, clk Word, w With RPT, clk Class 2 1 N/R 7a vector8 VCALL Execution Push PC + 1 PC ⇐ *(0x7F00 + vector8) R7 ⇐ R7 + 2 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 VCALL vector8 1 1 1 1 1 1 1 0 1 7 6 5 4 3 2 1 0 vector8 Description Unconditional vectored call (Macro call).
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions See Also XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NOTACS Example 4.14.84.1 XOR A1, A1, 0x13FF XOR immediate value 0x13FF to A1 and store result in A1. Example 4.14.84.2 XOR A0, A0, 2, ++A Pre–increment pointer AP0, then XOR immediate value 2 to new A0 and store result in A0. Example 4.14.84.3 XOR A1, A1~, A1 XOR accumulator A1 to accumulator A1~, put result in accumulator A1. Example 4.14.84.
Individual Instruction Descriptions 4.14.85 XORB Logical XOR Byte Syntax [label] name dest, src Clock, clk Word, w With RPT, clk Class XORB An, imm8 1 1 N/R 2a Execution An ⇐ An XOR imm8 PC ⇐ PC + 1 (for two operands) Flags Affected dest is An: OF, SF, ZF, CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 XORB An, imm8 0 0 1 0 1 1 0 9 8 7 6 5 An 4 3 2 1 0 imm8 Description Bitwise logical XOR lower 8 bits of An and dest byte.
Individual Instruction Descriptions 4.14.
Individual Instruction Descriptions 4.14.87 ZAC Zero Accumulator Syntax [label] name dest [, mod] ZAC An[~] [, next A] Execution [premodify AP if mod specified] dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 ZAC An[~] [, next A] 1 1 1 0 0 11 Clock, clk Word, w With RPT, clk Class 1 1 nR+3 3 10 next A 9 8 An 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ~A Description Zero the specified accumulator.
Individual Instruction Descriptions 4.14.88 ZACS Zero Accumulator String Syntax [label] name dest Clock, clk Word, w With RPT, clk Class ZAC An nS+3 1 nR+3 3 Execution dest ⇐ 0 PC ⇐ PC + 1 Flags Affected ZF = 1 Instructions 16 15 14 13 12 11 10 ZACS An[~] 1 1 1 0 0 1 1 9 8 An Description Zero the specified accumulator string. See Also ZAC 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 ~A Example 4.14.88.
Instruction Set Encoding 4.
Instruction Set Encoding Instructions 16 15 14 13 12 11 10 CMP An, {adrs} 0 1 0 1 1 0 0 1 8 7 6 5 4 An 3 2 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 7 6 5 1 0 JMP pma16, Rx–– 1 0 0 0 0 0 0 1 0 1 0 1 Rx 1 0 JMP pma16, Rx++R5 1 0 0 0 0 0 0 1 0 1 Rx 1 1 0 0 0 JMP *An 1 0 0 0 1 0 0 Jcc pma16 1 0 0 0 0 0 Not An 0 0 0 0 0 Not 1 MOV {adrs}, An[~] [, next A] 0 0 0 0 0 0 0 0 0 0 1 1 A~ 0 MOV An[~], imm16 [, next A] 0 0 0 0 0 Rx 0 1 0 Not Rx 1 0 Rx 1 1 cc 0 Not cc pma16 next A An adrs dma16
Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 MOV PH, {adrs} 1 1 0 1 1 0 0 0 1 MOV MR, {adrs} 1 1 0 1 0 1 MOV TOS, {adrs} 1 MOV {adrs}, PH 1 1 0 1 0 1 0 1 0 MOV {adrs}, STR 1 MOV {adrs}, DP 1 1 0 1 0 1 0 1 0 MOV {adrs}, TOS 1 MOV STR, {adrs} 1 0 0 1 0 1 0 1 1 0 1 APn 0 adrs 1 1 1 1 1 adrs 1 1 1 0 0 1 adrs 0 1 0 0 0 0 adrs 1 1 0 1 0 0 adrs 0 1 0 0 0 1 adrs 0 1 0 0 0 1 adrs 1 1 0 1
Instruction Set Encoding Instructions 16 15 14 MOVB {adrs}, An x MOVB An, imm8 1 0 1 0 0 0 1 An imm8 MOVB MR, imm8 1 0 1 0 1 1 1 An imm8 MOVB Rx, imm8 1 0 1 1 1 0 k4 MOVBS An, {adrs} 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 9 8 7 6 5 4 3 2 1 0 k3 k2 k7 k6 k5 An Rx k1 k0 adrs 1 0 0 An 1 adrs 0 A~ 1 An 1 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
Instruction Set Encoding Instructions 16 15 14 13 12 11 10 9 8 MUL {adrs} 1 1 0 1 1 1 0 1 1 MULR {adrs} 1 1 0 7 6 5 4 3 2 1 0 A~ 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.13] x 1 1 1 0 1 adrs 0 dma16 (for direct) or offset16 (long relative) [see section 4.13] x MULS An[~] 1 1 1 0 0 1 1 An MULAPL An, {adrs} 0 1 1 0 1 1 0 An 1 1 1 1 0 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
Instruction Set Encoding Instructions 16 15 14 13 12 11 10 7 6 5 4 3 2 ORS An[~], An[~], pma16 1 1 1 0 0 1 1 9 An 8 1 0 0 0 0 1 A~ ~A ORS An[~], An~, An 1 1 1 0 0 1 1 An 0 1 0 0 1 0 A~ ~A OUT port4, {adrs} 1 1 0 0 1 port4 1 0 adrs dma16 (for direct) or offset16 (long relative) [see section 4.
Instruction Set Encoding Instructions 16 15 14 13 12 11 10 7 6 5 4 3 2 SHLTPLS An[~], An[~] 1 1 1 0 0 1 1 9 An 8 1 1 0 1 0 0 A~ ~A SHLAC An[~], An[~] [, next A] 1 1 1 0 0 next A An 0 0 1 1 0 0 A~ ~A SHLACS An[~], An[~] 1 1 1 0 0 1 1 An 0 0 1 1 0 0 A~ ~A SHRAC An[~], An[~] [, next A] 1 1 1 0 0 next A An 0 1 0 1 1 0 A~ ~A SHRACS An[~], An[~] 1 1 1 0 0 1 1 0 1 0 1 1 0 A~ ~A STAG {adrs} 1 1 0 1 0 1 1 An 0 1 0
Instruction Set Encoding Instructions 16 15 14 13 12 11 7 6 5 4 3 2 1 0 ZAC An[~] [, next A] 1 1 1 0 0 next A An 0 0 0 1 1 0 0 ~A ZACS An[~] 1 1 1 0 0 1 An 0 0 0 1 1 0 0 ~A cc names cc 10 1 9 8 Description Tr e condition (Not True N t tr true e condition) cc name Not cc name Z NZ Conditional on ZF=1 (Not condition ZF=0) 0 0 0 0 0 0 0 0 0 1 S NS Conditional on SF=1 (Not condition SF=0) 0 0 0 1 0 C NC Conditional on CF=1 (Not condi
Instruction Set Summary 4.16 Instruction Set Summary Use the legend in Section 4.13 and the following table to obtain a summary of each instruction and its format. For detail about the instruction refer to the detail description of the instruction.
Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk CMP Rx, imm16 2 2 N/R 2b CMP An[~], An[~] [, next A] 1 1 N/R 3 CMP An[~], imm16 [, next A] 2 2 N/R 4c CMP Rx, R5 1 1 N/R 4d CMPB An, imm8 1 1 N/R 2a CMPB Rx, imm8 1 1 N/R 4b CMPS An, {adrs} Table 4–46 1b CMPS An[~], pma16 Table 4–46 Class nS+4 2 N/R 2b nS+3 1 nR+3 3 CMPS An, An~ CMPS An~, An COR An, *Rx 3 1 3(nR+2) 9a CORK An, *Rx 3 1 3(nR+2) 9a
Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk MOV {adrs}, An[~] [, next A] Table 4–46 Table 4–46 1a MOV An[~], {adrs} [, next A] Table 4–46 Table 4–46 1a MOV {adrs}, *An Table 4–46 Table 4–46 1b MOV An[~], imm16 [, next A] 2 2 N/R 2b MOV MR, imm16 [, next A] 2 2 N/R 2b MOV An, An~ [, next A] 1 1 nR+3 3 MOV An[~], PH [, next A] 1 1 nR+3 3 MOV SV, An[~] [, next A] 1 1 nR+3 3 MOV PH, An[~] [, next A] 1 1 nR+3 3 MOV An[~], *An[~] [,
Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w MOV {adrs}, SV Table 4–46 Table 4–46 5 MOV {adrs}, APn Table 4–46 Table 4–46 5 MOV {adrs}, TOS Table 4–46 Table 4–46 5 MOV STR, {adrs} Table 4–46 Table 4–46 5 MOV {flagadrs}†, TFn 1 1 nR+3 8a MOV TFn, {flagadrs}† 1 1 nR+3 8a MOV TFn, {cc} [, Rx] 1 1 N/R 8b MOV STR, imm8 1 1 N/R 9b MOV APn, imm5 1 1 N/R 9c MOVB An, {adrs}† Table 4–46 Table 4–46 1b MOVB {adrs}†, An Table
Instruction Set Summary name dest [, src] [, src1] [,mod] MOVU MR, {adrs} Table 4–46 Table 4–46 5 MOVAPH An, MR, {adrs} Table 4–46 Table 4–46 1b MOVAPHS An, MR, {adrs} Table 4–46 Table 4–46 1b MOVSPH An, MR, {adrs} Table 4–46 Table 4–46 1b MOVSPHS An, MR, {adrs} Table 4–46 Table 4–46 1b MUL An[~] [, next A] nR+3 3 MUL {adrs} Table 4–46 Table 4–46 5 MULR {adrs} Table 4–46 Table 4–46 5 MULS An[~] nR+3 3 MULAPL An, {adrs} Table 4–46 1b MULAPL An[~], An[~] [, n
Instruction Set Summary name dest [, src] [, src1] [,mod] Clock, clk Words, w With RPT, clk OR TFn, {flagadrs} 1 1 nR+3 8a OR TFn, {cc} [, Rx] 1 1 N/R 8b ORB An, imm8 1 1 N/R 2a ORS An, {adrs} Table 4–46 1b ORS An[~], An[~], pma16 nS+4 2 N/R 2b ORS An[~], An~, An nS+3 1 nR+3 3 OUT port4, {adrs} nR+3 6a OUTS port6, An[~] nR+3 6b RPT {adrs}8 N/R 5 RPT imm8 Table 4–46 Table 4–46 nS+3 1 Table 4–46 Class 1 1 N/R 9b 1 1 N/R 5 1 1 nR+3 8a RFM
Instruction Set Summary name dest [, src] [, src1] [,mod] SHLTPLS An, {adrs} SHLTPLS An[~], An[~] SHLAC An[~], An[~] [, next A] SHLACS An[~], An[~] SHRAC An[~], An[~] [, next A] SHRACS An[~], An[~] STAG {adrs} SOVM Clock, clk Words, w Table 4–46 With RPT, clk Class Table 4–46 1b nS+3 1 nR+3 3 1 1 nR+3 3 nS+3 1 nR+3 3 1 1 nR+3 3 nS+3 1 nR+3 3 Table 4–46 5 N/R 9d Table 4–46 1a Table 4–46 1 1 SUB An[~], An, {adrs} [, next A] SUB An[~], An[~], imm16 [, nex
Instruction Set Summary name dest [, src] [, src1] [,mod] XORS An, {adrs} XORS An[~], An[~], pma16 nS+4 XORS An[~], An~, An ZAC An[~] [, next A] ZACS An[~] cc names Clock, clk Words, w With RPT, clk Class Table 4–46 1b 2 N/R 2b nS+3 1 nR+3 3 1 1 nR+3 3 nS+3 1 nR+3 3 Table 4–46 Description p True Condition (Not true condition) cc name Not cc name Z NZ Conditional on ZF=1 (Not condition ZF=0) S NS Conditional on SF=1 (Not condition SF=0) C NC Conditional on CF=1
4-204 8 8 8 8 8 8 8 8 8 8 16 8 16 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x2FA 0x30 8 0x00 0x04 Bits Address Name Assembly Language Instructions DAC Data RTOTRIM ‡MSP C l MSP50C614 only Port G Data ((output only) l ) Port F Data (i (input only) l ) Port E Control Port E Data (bidi (bidirectional) i l) Port D Control multifunction l if i controll Port D Data multifunction l if i port (bidirectional) Port C Control Port C Data (bidirectional) (bidi i l) Por
16 16 16 16 0x3D 0x3E 0x3F 8 0x39 16 16 0x38 0x3B 4 0x34 0x3A Bits Address Timer 2 preset Timer 2 period Clock S Speed d Control Timer 1 preset Timer 1 period Interrupt Flag Register Interrupt G l General Control DAC Control Name R/W R/W W R/W R/W R/W R/W R/W R/W T4 D5 D4 D3 PF PD 0 1 EP AR CE CE PD EP T2 I I T1 M M T T I I 0 = disable 1 = enable M M Resistor Trim bits T3 T T E1 E2 S1 S2 E2 11 E E T0 E E Function 8 S2 S1 Timer1 source T
Assembly Language Instructions Vector Source Trigger Event Priority Comment INT0 0x7FF0 DAC Timer timer underflow used to synch.
10 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference) DAC Precision IntGenCtrl PDMCD Bit 8 bits 1 0 9 bits 1 0 10 bits 1 Master Clock Rate (Hz) PDM Rate (Hz) CPU Clock Rate (Hz) Output Sampling Rate (Hz) Number of Instructs btwn DAC Interrupts Number of Instructs btwn 10 kHz Interrupts 1x 0x 13 2.62 M 2.62 M 1.31 M 10.24 k 128 128 2x 0x 26 5.11 M 5.11 M 2.56 M 19.97 k 128 256 4x 0x 4D 10.22 M 10.22 M 5.11 M 39.94 k 128 512 8x 0x 9B 20.45 M 20.45 M 10.
Instruction Set Summay 4-208 Assembly Language Instructions
Chapter 5 Code Development Tools For code development purposes, the programmable MSP50P614 is used. The MSP50C6xx code development tool is used to compile, link, and debug assembly language programs. This tool can also be used to program an MSP50P614. A reduced function C compiler, (called C– –) is also available. Topic Page 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 5.2 MSP Software Development Tool . . . . . . . . . . . .
Introduction 5.1 Introduction The MSP50C6xx development tools gain access to the core controller via a serial scan interface called the Scanport. The basic elements needed to do development with the MSP50C6xx devices are listed below in Section 5.3. The MSP50C6xx software development tool is included with the MSP scanport interface (TI part #MSPSCANPORTI/F) or MSPSI. The mask programmed MSP50C6xx devices are available in die form to support large volume production quantities.
MSP50C6xx Software Development Tool the reset circuit and the reset pin, and connecting the scanport reset signal directly to the reset pin. See the recommended reset circuit shown in Figure 1–3. It is also recommended that all production boards be built with the scanport interface connector footprint connected to the appropriate pins and VPP-level translator circuit shown in Figure 5–1. This allows the MSP50C6xx Software Development Tools to facilitate any post production debugging.
Requirements 5.3 Requirements The requirements for a complete MSP50C6xx development system are as follows: PC Requirements: - Intel i486 or Pentium class processor Microsoft Windows 3.
Hardware Installation 5.4 Hardware Installation The following steps are used to set up the hardware (see Figure 5–2): 1) Connect the 18 V power supply to the MSPSI and connect the mains pins to a 120 V, 60 Hz ac source. 2) Connect one end of the IEEE1284 parallel cable to the MSPSI board and the other end to the PC parallel port. The red (power) LED should be ON. The yellow (Emul/Prog) LED comes ON when entering into emulation mode or during programming.
Software Installation Figure 5–3. 10-Pin IDC Connector (top view looking at the board) 10-PIN HEADER (3M PART# 2510–60024B) 0.35I IDC2X5M IDC2X5M VPP 1 2 RESET PGMPULSE 3 4 SCANCLK GND 5 6 SYNC SCANIN 7 8 N/C SCANOUT 9 10 VDD PAD DIA 0.060I 0.800I HOLE DIA 0.038I 0.1I 0.1I PINOUT DETAILS LAYOUT DETAILS 5.5 Software Installation Install the MSP50P614/MSP50C614 development tool from the supplied floppy disk by running the setup.exe.
Software Installation Figure 5–5. Setup Window Step 2: After setup runs the InstallShield (see Figure 5–4), the setup window pops up (see Figure 5–5). Step 3: Press the Next > button to continue with installation or press Cancel to exit installation.
Software Installation Figure 5–6. Exit Setup Dialog Step 4: If you press Cancel, you can return to setup by pressing Resume button. You can exit setup by pressing Exit Setup button (Figure 5–6). Figure 5–7.
Software Installation Step 5: If you continue with setup, you will be brought to User Information dialog. Enter your Name and Company Name in the two respective fields. To get into this screen, you must press yes to the license screen and press next to the Information dialog. Step 6: Type any alphanumeric value as Serial number. Press Next > when done. Press < Back to go to the previous dialog. Press Cancel to exit. Figure 5–8.
Software Installation Figure 5–9. Select Program Folder Dialog Step 9: Enter a new folder name in Select Program Folder dialog. Step 10: Press Next > to continue with installation.
Software Installation Figure 5–10. Copying Files Step 11: The program starts installation. When the installation is complete, an icon is also created on the desktop.
Software Installation Figure 5–11.Setup Complete Dialog Step 12: The Setup Complete dialog message is displayed when setup is completed. Press the Finish button to complete the installation.
Software Emulator 5.6 Software Emulator Run the EMUC6xx.exe program which will be in the installation directory or on your desktop (icon). Your scanport interface and the target board must be connected and turned on before the emulator can be successfully used. If the opening window comes up without any messages, the system is working properly. If the ”WARNING Development board not detected” message appears, there is a communication problem between the PC and the board.
Software Emulator Figure 5–13. Project Menu Figure 5–14.
Software Emulator Figure 5–15. File Menu Options 5.6.2 Projects The emulator can only work from project files created within the emulator itself. These files have the extension .rpj, and are not compatible with the .rpj files used in the old simulator. In other words, even to assemble a single assembly program, the user has to create a project and insert the name of the assembly file in the project. To create a new project: Menu Project/New Project, then enter a project name (Figure 5–14).
Software Emulator (pfe32.exe) and an error dialog. The user can modify the source code and save the changes, before restarting the building action. 5.6.3 Description of Windows Once a new project is created or an old project is opened, the following seven windows pops open (Figure 5–16). Figure 5–16.
Software Emulator Figure 5–17. RAM Window RAM Window : Displays 16-bit data memory hex values. The left most column is the address. Data memory is always addressable as bytes by MSP50C614 instructions. Each value displayed in this window is actually two consecutive byte data. Data memory values consist of the usual 16 bits, plus a 17th bit called the tag bit. If the tag bit is set, the background is yellow, otherwise it is white.
Software Emulator Watch Window : Watch window displays the data memory location and data to be watched. It mirrors the value displayed in the RAM window. The Watch window is provided as a help to display locations that may not be visible in the RAM window without scrolling. See Ram Window above to know more about how to use Watch window. Figure 5–18. CPU Window CPU Window : Displays values in all MSP50P614/MSP50C614 system registers and some additional information.
Software Emulator being run in emulation mode. STK field is the depth of the stack. The emulator keeps track of number of calls and returns and changes this variable accordingly. CUR field is the current subroutine name. In C–– programs it becomes very handy to display local variables of a subroutine. C– – Figure 5–19. Program Window Program Window : The program window displays program instructions, comments, preprocessor text, and program memory location.
Software Emulator background is the line reached by a search command (by PC, line number or label). Search position can also be set by double clicking on it in the program window. The line (if any) contain the hardware breakpoint is displayed in green background. To set a hardware breakpoint, just click the right mouse button over the line you want to break, while holding the SHIFT key down. Only program lines that are not in a gray area can contain breakpoints.
Software Emulator variable value and its address in RAM are then displayed (Figure 5–21). Variables appearing on a gray background either are not defined, or are not active at this time. The user can also use the Inspect option in the Debug menu to insert a variable in the Inspect window. Figure 5–21. Inspect Dialog Figure 5–22.
Software Emulator modified (i.e, by double clicking on a value and typing its new hexadecimal value over the existing value). Values of read only registers cannot be modified. Figure 5–23. I/O Ports Window Project Window : All source files making up the project are displayed in this window. Only assembly language files (.asm) and C– – source files (.cmm) should be inserted in a project. To insert a file, activate the project window by positioning the mouse over it, and hit the INS key.
Software Emulator Step Over : This menu option, (key equivalent: F8), allows the user to step over a call instruction in the program window. Note that the program window does not need to have the focus to execute a Step instruction. If the Step Over instruction leads into a gray area, i.e., a program line, or group of program lines that cannot be stepped into, the system automatically execute the instructions until it gets out of the gray area.
Software Emulator Fast Run : This menu option, (key equivalent: CTRL+F9), allows the user to execute a portion of the program window, until a breakpoint is encountered. The windows are not refreshed until the program stops, so that the execution speed is maximized. If no breakpoint is encountered, the user can stop the program by hitting the STOP option (CTRL+F10) in the debug menu.
Software Emulator Figure 5–25.
Software Emulator Trace Mode : This menu option launches the Trace Mode Dialog (Figure 5–25), that allows that user to run the chip in trace mode, i.e., running an internal program on the chip while monitoring its execution on the scanport. Figure 5–26. Trace Mode Optional Trace Mode start program memory location (hex). If this value is not provided, execution starts from current PC value. Optional PC location where execution should stop.
Software Emulator Stop Internal : This menu option halts execution of an internal program. It provides an internal picture of the chip at the time the internal program execution was halted. Note that due to the asynchronous nature of this halt, one erroneous instruction may be executed before the chip actually stops. For the MSP50P614/MSP50C614 chip, it restarts the emulation mode and reads the CPU and RAM values.
Software Emulator Init RAM : Initializes the data memory values to zero including tag bits. Init Registers : Initializes all the system registers (excluding accumulators) to zero except PC which is initialized to start vector. Init Accumulators : Initializes all the accumulators to zero. Init All : This menu option initializes all internal registers and all RAM location in the chip. It also resets the cycle counter. The program counter is set at the value indicated by the start vector at address 0x7FFF.
Software Emulator Figure 5–28. Options Menu Figure 5–29. Miscellaneous Dialog List of directories separated by semicolons that the C–– compiler will search for include files enclosed in angle brackets (<>) before searching current directory. Heap start address for C–– compiler. Beginning of Stack for C–– compiler. Parallel port address where the Scanport interface is connected.
Software Emulator Figure 5–30. Windows Menu Options 5.6.7 Emulator Online Help System The emulator has an online help which is launched when the Help menu option is left clicked with a mouse. The help window (Figure 5–30) is context sensitive and graphical in nature. Any topic selected by pointing the mouse to the topic and clicking the left mouse button. If a help is available on the topic, the cursor becomes a hand cursor. Some help topics launches more context sensitive help windows.
Software Emulator Figure 5–31.
Software Emulator 5.6.8 Known Differences, Incompatibilities, Restrictions - 5-32 Include statements in assembly language files must enclose the file name in double quotes. REF/DEF statements in assembly language files should be replaced with EXTERNAL/GLOBAL statements, but the old REF/DEF are still supported. There is no default type for variables in the C– – compiler. The user should always use int or char.
Assembler 5.7 Assembler The MSP50P614/MSP50C614 assembler is implemented as a Windows DLL (Dynamic Linked Library). 5.7.1 Assembler DLL The current name of the DLL file is asm6xx.dll. It can be invoked from any Windows program, provided that the user included the file called asm6xx.lib in the Windows project. The syntax of the call is: extern int FAR PASCAL ASM_MAIN (LPSTR source_file, short *warn,short *errpass1,struct error_struct *,LPSTR include_list); /* ....
Assembler 5.7.2 Assembler Directives Assembler directives are texts which have special meaning to the assembler. Some of these directives are extremely helpful during conditional compiling, debugging, adding additional features to existing codes, multiple hardware development, code release etc. Other directives are an essential part of the assembler to initialize variable with values, assigning symbols to memory location, assigning origin of a program, etc.
Assembler symbol is any alphanumeric text starting with an alphabetic character, a number, or an expression. Examples: SYM1 EQU (12 * 256) SYM2 EQU SYM1 * (32 / 4) SYM3 EQU SYM1 * SYM2 – *0x200 From the above example SYM1, SYM2 and SYM3 are symbols for some expression. The grammar for Symbol is as follows: symbol: expression | symbol Expression Restrictions: It is recommended that a space be inserted between the operator (i.e.
Assembler Example: #IF expression ; do something here #ELSE ; do other things here #ENDIF #IFDEF symbol: Start of a conditional assembly structure. If symbol has been defined (either with a #DEFINE directive or an EQU directive) then the lines following this directive are assembled until a #ELSE or a #ENDIF directive are encountered. If symbol has not been defined, then all input lines are skipped until a #ELSE or a #ENDIF directive is encountered.
Assembler BYTE expression[,expression]: Introduces one or more data items, of BYTE size (8 bits) . The bytes are placed in the program memory in the order in which they are declared. CHIP_TYPE chip_name: This directive is here for compatibility with future chips in the same family. It defines some chip parameters (like RAM and ROM size) for the assembler. For now, the only defined chip names are MSP50P614/MSP50C614 and MSP50P614/MSP50C614.
Linker should be declared there as EXTERNAL (or REF). Note that this technique can also be used to make constants defined with the EQU statement available to other files. INCLUDE filename: This directive is used to insert another file in the current assembly file. The name of the file to be included must be enclosed in double quotes.
C– – Compiler The syntax of the call is: extern int FAR PASCAL LINK_MAIN (LPSTR source_file,LPSTR exe_file); ..... ierr=LINK_MAIN (source_file,exe_file); Where: - source_file is the project file name, which contains the names of the files to be linked. exe_file is the name of the linked executable file. ierr is the total number of errors returned by the linker. If errors occur during link, the error information is placed in a file with extension .rer, with the same name as the executable file. 5.
C– – Compiler short ram_size; short verbose; short c_code; short optimize; char dir_list; char directory[MAX_LEN]; /* /* /* /* /* /* /* /* /* ram size for the chip */ refers to assembly code output */ if non zero, c code is included as */ assembly language comments */ should always be non zero */ string of include directories searched */ for C– – include directive */ name of data directory, i.e directory */ where tools where installed */ }; struct error_struct error_list[MAX_ERRORS]; /* ...
C– – Compiler 5.9.
C– – Compiler 5.9.4 C– – Directives C– – has a limited number of directives and some additional directives not found in ANSI C compilers. The following directives are recognized by the compiler. 5.9.4.1 #define This directive is used to introduce 2 types of macros, in typical C fashion: Without Arguments: defines a replacement string for a given string Example: #define PI 3.1415926535 Every occurrence of the token PI will henceforth be replaced with the string 3.1415926535.
C– – Compiler 5.9.4.3 #include As in regular C, this directive allows for the insertion of a file into the current file. If the file name that follows is enclosed in < >, the system searches the include directories for the file, otherwise, if it is enclosed in “ ”, the current directory is searched. Example: #include “file.h” #include The include directories are defined on the cmm_input structure passed to the compiler. There is no limit to the nesting of include files. 5.9.4.
C– – Compiler 5.9.5 Include Files There are currently two include files supplied with C– –, cmm_func.h, which contains function prototypes for the C– –functions and cmm_macr.h which contains some predefined macros.
C– – Compiler 5.9.6 Function Prototypes and Declarations As mentioned above, C– – function prototypes and declarations MUST be preceded with the keyword cmm_func. Also, since all functions return through accumulator A0, all functions are of type integer, so that the function type can be omitted in the function declaration. If present, it is ignored anyway. Trying to typecast a function as returning a pointer will result in a compiler error.
C– – Compiler Table 5–1. String Functions add_string(int *result,int *str1,int *str2,int lg)adds strings str1 and str2, of length lg (+2), and puts the result in string result sub_string(int *result,int *str1,int *str2,int lg) subtracts strings str2 from str1, of length lg (+2), and puts the result in string result. mul_string(int *result,int *str1,int mult,int lg1,int lgr)multiplies string str1 of length lg1 (+2) by integer multiple, and puts the result in string result, of length lgr (+2).
C– – Compiler Also note that the user has to supply the length of the input string and the length of the output string in the string multiply operations: the result of multiplying a string by an integer can be one word longer than the input string. Unpredictable results may occur if parameter lgr is not at least equal to lgr+1. 5.9.11 Constant Functions The only two constant functions implemented in C– – are xfer_const and xfer_single.
Implementation Details 5.10 Implementation Details This section is C– – specific. 5.10.1 Comparisons We use the CMP instruction for both signed and unsigned comparisons. The two integers a and b to be compared are in A0 and A0~.
Implementation Details - Unsigned comparison of a and b. (a is in A0, b is in A0~) Assembly Test Condition _ult a= b !AULT _ugt a>b AUGT The small number of comparisons was an invitation to use them as vector calls. We return a 1 or 0 in A0 as the result of the comparison, and also set flag 2 if the comparison is true. The flag is not currently used by the compiler.
Implementation Details 5.10.2 Division The integer division currently requires the use of several accumulator pointers. We divide a 16 bit integer located in A0 by a 16 bit integer located in A0~. We return the quotient in A0~, and the remainder in A0. We make use of A3~ and A3 for scratch pads. We also set flag 1 if a division by zero is attempted, and zero out the quotient and the remainder in this case. We also use PH for temporary storage of the divisor. 5.10.
Implementation Details Function declarations ( or function prototypes) are introduced by the mnemonic cmm_func. We only allow the new style of function declarations /prototypes, where the type of the arguments is declared within the function’s parentheses. For example: cmm_func bidon(int i1,char *i2) is valid, but: cmm_func bidon(i1,i2) int i1,char *i2; is invalid.
Implementation Details constant int M1[4]={0x04CB,0x71FB,0x011F,0x0}; constant int M2[4]={0x85EB,0x8FD9,0x08FB,0x0}; cmm_func string_multiply(int *p,int lgp,int *m1,int lgm1,int *m2,int lgm2) { /* note: length of p,(lgp+2) must be at least (lgm1+2) + (lgm2+2) +1 */ /* this function string multiplies string m1 of length lgm1+2 by string m2 of length lgm2+2, and puts the result into string p, of length lgp+2 */ int sign,i,j; int *mm1,*mm2,*pp; sign=1; mm1=calloc(sizeof(int),lgm1+2); mm2=calloc(sizeof(int),lg
Implementation Details free(mm2); free(pp); } cmm_func main(int argc,char *argv) { int m1[4],m2[4],product[9]; xfer_const(m1,M1,STR_LENGTH(4)); xfer_const(m2,M2,STR_LENGTH(4)); string_multiply(product,STR_LENGTH(9),m1,STR_LENGTH(4),m2,STR_LENGTH(4)); } 5.10.5 Programming Example, C –– With Assembly Routines There are several important considerations when using the C– – compiler. The ram allocation must be coordinated so that a location is not accidentally used twice.
Implementation Details find the correct size for bogus. Bogus can be made larger for extra safety as long as enough memory is left over for the C– – variables and the stack. If space allows, it is a good idea to add a few extra words to bogus in case assembly variables are added to the project without modifying bogus. It is also important not to alter the contents of registers R5 and R7. R7 is the stack pointer and R5 is a frame pointer used in C to C function calls.
Implementation Details | | |––––––––––––––| | R7 | |––––––––––––––| |R7 | | | |––––––––––––––| |R5,R7 | | |––––––––––––––| |––––––––––––––| |––––––––––––––| | | | | | | |––––––––––––––| |––––––––––––––| |––––––––––––––| | | |(old)R5 | R5 | |<– This is the SP |––––––––––––––| |––––––––––––––| |––––––––––––––| before the | | |(old)R5 | R5 | |C function call.
Implementation Details C to C function return (in cmm_return).
Implementation Details R7,R5 |––––––––––––––| | | |––––––––––––––| | | |––––––––––––––| | | |––––––––––––––| |(old)R5 | |––––––––––––––| |(old)R5 | |––––––––––––––| |Return Addr | |––––––––––––––| |Return Addr | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 1 | |––––––––––––––| |Param 1 | |––––––––––––––| |Stack data | |––––––––––––––| SUBB R7,4 Code Development Tools 5-57
Implementation Details C to ASM function call. The stack is shown after the operation on the bottom is performed.
Implementation Details R7 R5 | | |––––––––––––––| | | |––––––––––––––| | | | | |––––––––––––––| | | |––––––––––––––| |Return Addr | |––––––––––––––| |Return Addr | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 2 | |––––––––––––––| |Param 1 | |––––––––––––––| |Param 1 | |––––––––––––––| |Stack data | |––––––––––––––| Function call C to ASM function return R7 R5 | | |––––––––––––––| | | |––––––––––––––| | | |––––––––––––––| | | |––––––––––––––| | | |––––––––––––––| |Return Addr | |––––––––––––––|
Implementation Details To call an assembly routine from C– –, the routine must be defined as GLOBAL in the assembly file and as a CMM_FUNC in the C– – file. The following contains C– – callable assembly routines for accessing the I/O ports, and a wait routine. A C– – program which calls the assembly routines is also provided.
Implementation Details ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ; called from C–– ; void oport(char Port, int Data) ; Writes Data to the I/O port specified by the letter Port. ; Example: ; oport(’B’, 0xAA); //Write 0xAA to port B.
Implementation Details _iprtc in ret a0, 0x10 ; read from PortC in ret a0, 0x18 ; read from PortD in ret a0, 0x20 ; read from PortE _iprtd _iprte _iprtf in a0, 0x28 ; read from PortF ret _in_port_access ; table for table lookup DATA _iprta DATA _iprtb DATA _iprtc DATA _iprtd DATA _iprte DATA _iprtf ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ; called from C–– ; void cport(char Port, int Control) ; Writes Control bits for the I/O p
Implementation Details DATA _cprte ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ; called from C–– ; void wait(int msec) ; waits for the amount of msec passed ; Calls: wait1ms ;––––––––––––––––––––––––––––––––––––––––––––––––––––– _wait mov a0, *r7 – 2 shlac a0, a0 mov *tempa, a0 mov r4, *tempa _rep call wait1ms ;wait 1ms jrnzp _rep,r4–– ;decrement counter by 2 ret ;––––––––––––––––––––––––––––––––––––––––––––––––––––– ;***********************
Implementation Details nop ret ;**************************************************************** ; Dummy interrupt routines ;**************************************************************** DAC_ISR TIMER2_ISR TIMER1_ISR PORTD2_ISR PORTD3_ISR PORTF_ISR PORTD4_ISR PORTD5_ISR DUMMY_ISR nop INTE iret Here is a sample C–– file that accesses the routines. #ifdef DOC_FILE #******************************************************************************* #File: main.cmm # #Version: Release 1.
Implementation Details cmm_func iport(int x); // read a port int i,j,k,l; // various temp and loop variables int x[4]; // array holding the correct key sequence int locked=1; //variable returned by lock() cmm_func lock(){ x[0]= 0xEF; //MS7 x[1]= 0xBF; //MS9 x[2]= 0xEF; //MS7 x[3]= 0x7F; //MS10 locked=0; cport(’B’, 0xFF); //Configure port B as output. //Port B is the LED’s on the //code development unit. oport(’B’, 0xFF); //Turn off all 4 LEDs.
Implementation Details wait(100); oport(’B’, wait(100); oport(’B’, wait(100); oport(’B’, wait(100); oport(’B’, wait(100); 0x00); 0xFF); 0x00); 0xFF); } else{ // If the correct inputs were given.
Beware of Stack Corruption 5.11 Beware of Stack Corruption MSP50C614/MSP50P614 stack (pointed by R7 register) can easily get corrupted if care is not taken. Notice the following table read code: SUBB R7, 4 MOV A0, *R7–– ADD A0, address MOV A0, *A0 ADD A0, *R7–– MOV A0, *A0 RET This code will work perfectly well if no interrupts happen before SUBB and MOV instruction.
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Chapter 6 Applications This chapter contains application information on application circuits, processor initialization sequence, resistor trim setting, synthesis code, memory overlays, and ROM usage. Topic Page 6.1 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 6.2 MSP50C614/MSP50P614 Initialization Codes . . . . . . . . . . . . . . . . . . . . 6–4 6.3 Texas Instruments C614 Synthesis Code . . . . . . . . . . . . . . . . . . . . . . .
Application Circuits 6.1 Application Circuits Minimum Circuit Configuration for the C614/P614 Using Resistor-Trimmed Oscillator To pin 1 of Scan Port Connector† 5V (optional ) To pin 2 of Scan Port Connector† 0.
Application Circuits It is of particular importance to provide a separate decoupling capacitor for the VDD, VSS pair which services the DAC. These pins are pad numbers 21 and 19, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement.
MSP50C614/MSP50P614 Initialization Codes In any C614 application, it is important for certain components to be located as close as possible to the C614 die or package. These include any of the decoupling capacitors at VDD (0.1 µF). It also includes all of the components in the crystal-reference network between OSCIN and OSCOUT (22 pF, 10 MΩ, 32 kHz). 6.
MSP50C614/MSP50P614 Initialization Codes 6.2.1 File init.asm ;**************************************************************** ; INIT.ASM ; ; ; Copyright: 1998 Texas Instruments, Inc. All rights reserved. ; ; ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; This Initialization Routine has the following Dependent Files. ; These should be ”included” once within the MAIN program .
MSP50C614/MSP50P614 Initialization Codes out IntGenCtrl,a0 ;clear all interrupt mask bits, disable timers mov r0,0x000 ;point to beginning of RAM mov r4,RAM_SIZE – 2 ;do a loop RAM_SIZE times BEGLOOP rtag *r0 ;reset tag mov *r0++,a0 ;clear the RAM ENDLOOP mov STR,0 ;clear string register mov ap0,0 ;clear accum pointer 0 mov ap1,0 ;clear accum pointer 1 mov ap2,0 ;clear accum pointer 2 mov ap3,0 ;clear accum pointer 3 mov r0,0 ;clear register 0 mov r1,0 ;clear register 1 mov r2,0 ;clear register 2 mov r3,0
MSP50C614/MSP50P614 Initialization Codes mov *save_clkspdctrl,a0 ;save the ClkSpdCtrl value for later, when ;waking up from mid or deep sleep ;disable TIMER 2 mov 0~,TIM2REFOSC + TIM2IMR out IntGenCtrl,a0~ mov a0~,6553 ;setup a 200 ms period out TIM2,a0~ ;load TIM2 and PRD2 in one fell swoop mov a0~,TIM2ENABLE + TIM2REFOSC + TIM2IMR out IntGenCtrl,a0~ ;use 32 kHz crystal as source, wake up from TIM2 out ClkSpdCtrl,a0 ;set clock to full speed! idle ;go to sleep...
Texas Instruments C614 Synthesis Code 6.3 Texas Instruments C614 Synthesis Code Some sample codes are supplied with the development tools. These samples are in the .\Examples subdirectory where the tool is installed. In this manual only one example code is explained. This description applies to all the code development.
Texas Instruments C614 Synthesis Code To continue, click on the Run Internal icon again. The LEDs should flash during MELP synthesis (Extra, extra, read all about it) and should flash in a different pattern after MELP synthesis. Running the Program The MELP1 program can run on either the demo box or the code development board. The latter has only two switches (SW1 and SW2) while the former has ten switches (SW1 to SW10), four LEDs, an LCD, an EPROM socket and a flash card socket.
Texas Instruments C614 Synthesis Code | spk_ram.irx | | –––––––– melp | melp.obj | melp.irx | –––––––– modules | | | –––––––– 605 605.asm 605.irx | | –––––––– general | init.asm | sleep.asm | io_ports.irx | | –––––––– isr | dac_isr.asm | tim1_isr.asm | tim2_isr.asm | –––––––– ram | ram.irx | –––––––– speech | –––––––– melp | 1kbps.qfm | 24kbps.qfm | main.asm main.irx main_ram.irx melp1.
Texas Instruments C614 Synthesis Code File Description Util.obj Maths functions and tables used by the vocoders. Dsputil.asm Oversampling and miscellaneous functions. Getbits.asm Routine to get data from ROM. Speak.asm Routines to speak a phrase or sentence. Dsp_var.irx Various vocoder constants. Speak.irx Speech header constants. Spk_ram.irx RAM map of variables common to all vocoders. Melp.obj MELP object code. Melp.irx MELP include file. 605.
Texas Instruments C614 Synthesis Code RAM Usage The file MAIN.LST contains the variable RAM assignments. Do a search for BEGIN_RAM to find the start of the RAM locations. Adding Another Module There are three steps to adding a new module to a project. First, the project file (.RPJ) must be updated to include the ASM file (click on File – Insert to add files to a project). Second, the RAM overlay file MAIN_RAM.IRX should be updated with the RAM required by the new module.
Texas Instruments C614 Synthesis Code These files may be edited for special purpose code INIT.ASM and SPEAK.ASM These files should never be edited SLEEP.ASM, RAM.IRX and SPK_RAM.IRX A good rule of thumb to follow is that files under the DSP directory should be left alone, and all custom code should be added either to MAIN.ASM or to a new directory under MODULES, e.g., MODULES\CUSTCODE.
ROM Usage With Respect to Various Synthesis Algorithms 6.4 ROM Usage With Respect to Various Synthesis Algorithms The following table lists some possible synthesis options and their ROM requirements. The models assume that just enough program space, as necessary for storage of the synthesis algorithm, is used. The remainder of the ROM is dedicated entirely to the speech data, with the goal of maximizing the synthesis playback time. If any two synthesis algorithms are to be used in combination, e.g.
Chapter 7 Customer Information Customer information regarding package configurations, development cycle, and ordering forms are included in this chapter. Topic Page 7.1 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 7.2 Customer Information Fields in the ROM . . . . . . . . . . . . . . . . . . . . . . . . 7–7 7.3 Speech Development Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 7.
Mechanical Information 7.1 Mechanical Information The C614 is normally sold in die form but is also available in 100-pin PJM packages. The P614 is available in a windowed ceramic package, 120-pin PGA. NOTE: Scan Port Bond Out The Scan Port Interface on the MSP50C6xx devices has five dedicated pins and one shared pin that need to be used by the MSP50Cxx development tools. The SCANIN, SCANOUT, SCANCLK, SYNC, and TEST pins are dedicated to the scan port interface. The RESET pin is shared with the application.
Mechanical Information 7.1.2 Package Information The MSP50C614 will be available in the 100-pin PJM package (see Figure 7–1 and Table 7–1). Contact your local TI sales office for more information. Table 7–1.
Mechanical Information Figure 7–1. 100-Pin PJM Mechanical Information 0,38 0,22 0,65 80 0,13 M 51 50 81 12,35 TYP 100 14,20 13,80 17,45 16,95 31 1 30 18,85 TYP 20,20 19,80 23,45 22,95 0,16 NOM Gage Plane 2,90 2,50 0,25 0,25 MIN 0°– 7° 1,03 0,73 Seating Plane 3,40 MAX 0,10 4040022 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
Mechanical Information The C614 is sold in die form for its volume production. For software development and prototyping, a windowed ceramic 120 pin grid array packaged P614 is available. The P614’s PGA package is shown in Figure 7–2. Figure 7–2.
Mechanical Information The pin assignments for the 120-pin PGA are outlined in the following table. (Refer to Section 1.6 for more information on the signal functions.) Figure 7–3 provides a cross-reference between the C614 (die) pad numbers and the P614’s PGA package leads. Figure 7–3.
Customer Information Fields in the ROM 7.2 Customer Information Fields in the ROM In those cases where the customer code is programmed by Texas Instruments, some registration of the code-release is provided within the ROM. This information appears as 7 distinct fields within the ROM test-area. The ROM test-area extends from address 0x0000 to 0x07FF. The code-release information is stored in locations 0x0006 through 0x000C.
Speech Development Cycle 7.3 Speech Development Cycle Figure 7–4. Speech Development Cycle Speech Specification Speaker Selection Recording Script Preparation Speech Recording Software Design Software Writing Hardware Design Prototype Construction Speech Analysis Software Debugging Speech Editing Speech Evaluation System Evaluation A sample speech development cycle is shown in Figure 7–4.
Device Production Sequence All prototype devices are shipped with the following disclaimer: It is understood that, for expediency purposes, the initial 25 prototype devices (and any additional prototype devices purchased) were assembled on a prototype (i.e., not production-qualified) manufacturing line, whose reliability has not been characterized. Therefore, the anticipated inherent reliability of these devices cannot be expressly defined.
Ordering Information 7.5 Ordering Information Because the MSP50C614 is a custom device, it receives a distinct identification, as follows: CSM 614 Gate Code CSM: Custom Synthesizer With Memory Family Member XXX ROM Code X X Revision Letter Package or Die PJM: Loopin QFP (Preliminary) Y: Die 7.6 New Product Release Forms The new product release form is used to track and document all the steps involved in implementing a new speech code onto one of the parent speech devices.
New Product Release Forms NEW PRODUCT RELEASE FORM FOR MSP50C614 (DIE ONLY) SECTION 1. ORDER INFORMATION Division:____________________________ Company:___________________________ Project Name:________________________ Purchase Order #:_____________________ Management Contact: ___________________________ Phone:(___) ____________ Technical Contact : ___________________________ Phone:(___) ____________ Customer Code Version and Revision:____________________ (of format vv.
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Appendix AppendixAA MSP50C605 Preliminary Data This Appendix contains preliminary data for the MSP50C605 device. Note: MSP50C605 MSP50C605 is in the Product Preview stage of development. For more information contact your local TI sales office. Topic Page A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 A.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 A.
Introduction A.1 Introduction MSP50C605 is a spin off of the core processor MSP50C614. It uses three IO ports of MSP50C614 and maps a 1.835 Mbits of internal ROM. Using a 1 kbps MELP algorithm, the C605 can provide over 30 minutes of uninterrupted speech. There is no Port A and Port B control register in MSP50C605. Port DRD is read only, and Port DRP and DRA are write only. Apart from the additional ROM and corresponding IO port changes, all other functionality of the processor is similar to MSP50C614.
Architecture A.3.1 RAM The MSP50C605 (like MSP50C614) has 640 17-bit words of internal data memory (static RAM). This RAM occupies a space extending from 0 to 0x27F in the address space. A.3.2 ROM The MSP50C605 contains 32K by 17-bit words of internal program ROM and 229,376 bytes by 8 bits (i.e., 1,835,008 bits) of slow data ROM.
Architecture Figure A–1. MSP50C605 Architecture SCAN IN SCAN OUT SCAN CLK Scan Interface Break Point Emulation OTP Program Serial Comm. SYNC TEST PGM PULSE V SS V DD 5 5 Power (EP)ROM (P614 only) 32k x (16 + 1) bit Test–Area (reserved) 0x0000 to 0x07FF User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF (C605 only) (P614 only) DAC P DAC DAC M 32 Ohm PDM 0x30 V PP Resistor Trimmed 32 kHz nominal or or OSC OUT Crystal Referenced 32.
Architecture Figure A–2. MSP50C605 Memory Organization Program Memory Data Memory Peripheral Ports 0x0000 0x 0000 0x 00 DRD0–7 0x 08 DRP0–3 0x 10 PC0..7 data 0x 14 PC0..7 ctrl 0x 18 PD0..
Architecture Figure A–3.
Architecture Table A–1.
A-8
Appendix AppendixBA MSP50C604 Preliminary Data This Appendix contains preliminary data for the MSP50C604 device. Note: MSP50C604 MSP50C604 is in the Product Preview stage of development. For more information contact your local TI sales office. Topic Page B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2 B.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–2 B.
Introduction B.1 Introduction MSP50C604 is a spin off of the core processor MSP50C614. It is targeted as a slave device. An external microprocessor is needed to interface with MSP50C604 in slave mode. It can also be used a stand alone device if desired. B.
Architecture B.3.1 RAM The MSP50C604 (like MSP50C614) has 640 17–bit words of internal data memory (static RAM). This RAM occupies a space extending from 0 to 0x27F in the address space. B.3.2 ROM The MSP50C604 contains 32K by 17-bit words of internal program ROM. The program ROM space is divided into two areas: 1) The initial 2K words of ROM (0x0000 – 0x07FF) is reserved for built in selftest (BIST) that is provided by Texas Instruments during mass production.
Architecture Figure B–1. MSP50C604 Block Diagram SCAN IN SCAN OUT SCAN CLK Scan Interface Break Point Emulation OTP Program Serial Comm. SYNC TEST (C604 only) PGM PULSE (P614 only) DAC P DAC DAC M 32 Ohm PDM 0x30 V SS V DD 5 5 Power V PP (P614 only) (EP) ROM 32k x (16 + 1) bit Test–Area (reserved) 0x0000 to 0x07FF User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF Core Instr.
Architecture B.3.4 Slave Mode Operation The MSP50C604 is used as a peripheral device in slave mode. A microprocessor/microcontroller controls the R/WZ, STROBE, INRDY, OUTRDY pins of MSP50C604 to use it as a slave processor. No special programming is required to switchthe ’C604 to slave mode. Slave mode is exclusively controlled by the four pins mentioned above. B.3.5 Host Write Sequence 1) MSP50C604 signals readiness to receive data by taking INRDY low 2) Host takes R/WZ low.
Architecture Figure B–2. MSP50C604 Memory Organization and I/O ports Program Memory Data Memory 0x0000 0x 0000 Internal Test Code 2048 x 17 bit RAM 640 x 17 bit Peripheral Ports 0x 10 PC0..7 data 0x 14 PC0..7 ctrl 0x07FF 0x 18 PD0..7 data 0x0800 0x 1C PD0..
Architecture B.3.7 Interrupts Interrupts for MSP50C604 are the same as MSP50C614 in host mode except INT5 (port F interrupt) is not available. But in slave mode, INT3 and INT4 are external interrupts triggered by write sequence and read sequence as explained before.
Packaging B.4 Packaging The MSP50C604 is sold in die form. A 64 pin plastic package is also available. Table B–1.
Packaging Figure B–3. MSP50C604 Slave Mode Signals Host read sequence Host write sequence INRDY OUTRDY R/WZ STROBE Valid Data New Data PC0–PC7 Data latched to Port A Figure B–4.
Packaging B-10
Appendix AppendixCA MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed-signal processor. Topic C.1 Page MSP50C605 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.1 MSP50C605 Data Sheet This appendix contains the data sheet for the MSP50C605 mixed-signal processor.
