Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TSSOP 14 16-Bit 4 MHz I/O number 11

MSP430L092

MSP430C09x

SLAS673 –SEPTEMBER 2010

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Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFE0h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 4. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY

INTERRUPT

System Reset

Power-Up

WDTIFG

(1)

Reset 0x0FFFE 15, highest

External Reset

Watchdog

System NMI

SVMIFG, VMAIFG

(1)

(Non)maskable 0x0FFFC 14

Vacant memory access

User NMI

NMIIFG

(1)(2)

(Non)maskable 0x0FFFA 13

NMI

Timer1_A3 TA1CCR0 CCIFG0

(3)

Maskable 0x0FFF8 12

Timer1_A3 TA1CCR1 CCIFG1

(1)(3)

Maskable 0x0FFF6 11

Watchdog Timer_A Interval Timer Mode WDTIFG Maskable 0x0FFF4 10

A-Pool CxIFG Maskable 0x0FFF2 9

I/O Port P1 P1IFG.0 to P1IFG.6

(1)(3)

Maskable 0x0FFF0 8

Timer0_A3 TA0CCR0 CCIFG0

(3)

Maskable 0x0FFEE 7

Timer0_A3 TA0CCR1 CCIFG1

(1)(3)

Maskable 0x0FFEC 6

I/O Port P2 P2IFG.0 to P2IFG.3

(1)(3)

Maskable 0x0FFEA 5

0x0FFE8 4

Reserved Reserved

(4)

⋮ ⋮

0x0FFE0 0

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the

individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.