Datasheet

P1REN .x
00
01
10
11
P1DIR.x
00
01
10
11
P1OUT .x
from Module
TA0.2
TA1.2
P1SEL0.x
P1SEL1.x
0
1Vcc
Vss
P1IN.x
EN1
EN2
DModule X IN
#
from A -Pool
from A -Pool
P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3
P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3
Pad Logic
to A-Pool
PSELx=y # NSELx=y
PortsOn
P1IRQ.x
P1IE.x
P1IES.x Set
Q
P1IFG.x
MSP430L092
MSP430C09x
www.ti.com SLAS673 –SEPTEMBER 2010
Port P1, P1.2 and P1.3 Input/Output
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