Datasheet

P1REN.x
00
01
10
11
P1DIR.x
00
01
10
11
P1OUT.x
SMCLK
TA0.2
TA1.2
P1SEL 0.x
P1SEL 1.x
0
1Vcc
Vss
P1IN.x
P1IRQ.x
P1IE.x
P1IES.x Set
Q
Pad Logic
P1IFG.x
to A-Pool
PSELx=y # NSELx=y
P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN
to Clock System
EN1
EN2
DModule X IN
#
PortsOn
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010 www.ti.com
PORT SCHEMATICS
Port P1, P1.0 Input/Output
Table 12. Port P1 (P1.0) Pin Functions
CONTROL BITS/SIGNALS
(1)
PIN NAME (P1.x) x FUNCTION
RSELx/ASE
P1DIR.x P1SEL1.x P1SEL0.x
Lx
P1.0 (I/O) I:0, O:1 0 0 0
Timer_A0.2 1 0 1 0
Timer_A1.2 1 1 0 0
P1.0/TA0.2/TA1.2/ACLK/
0 ACLK 1 1 1 0
CCI0.1/A2/CLKIN
Timer A0, CCI1B 0 ≠0 ≠0 X
A2 X X X 2
CLKIN (via Bypass) X X X X
(1) X = Don't care
32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated