Datasheet

1
4
3
2
SPI_CS/TCK/P2.0/TA0.2/TA1.2/TA1.1
14
11
12
13
7
6
5
8
9
10
V
SS
/GND
P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3
/BOOST
P1.5/TA0.2/TA1.2/TA0.1
P1.6/TA0.2/TA1.2/TA1.1
V
CC
P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN
P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK
RST/NMI/SVMOUT
SPI_MISO/TDO/P2.3/TA0.2/TA1.2/CCI1.0
SPI_CLK/TDI/P2.2/TA0.2/TA1.2/CxOUT/CCI0.0
SPI_MOSI/TMS/P2.1/TA0.2/TA1.2/TA0.1
P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3
P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK
PW PACKAGE
(TOP VIEW)
2kB RAM
(128B+1792B
+96B)
Clock
System
2KB ROM
(Loader)
P2.0...P2.3GND/V
SS
MCLK
ACLK
SMCLK
I/O Port P2L
4 I/Os with
Interrupt
Capability
Watchdog
WDTA
32/16-Bit
Timer0_A3
3 CC
Registers
CPU &
Working
Registers
4W-JTAG
Analog-
Pool
Reset
Int-Logic
HF-OSC
Timer1_A3
3 CC
Register
V
CC
CLKIN
V
REF
TMS, TCK,
TDI, TDO
ULV-Ref.,
8-Bit ADC,
8-Bit DAC,
Comparator,
SVS
LF-OSC
ULV
Brownout
P1.0...P1.6
I/O Port P1L
7 I/Os with
Interrupt
Capability
RST/NMI/SVMOUT
Debug
support
CORE
MSP430L092
MSP430C09x
www.ti.com SLAS673 –SEPTEMBER 2010
Pin Designation, MSP430L092PW
Functional Block Diagram, MSP430L092PW
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