Datasheet

1
4
3
2
TCK/P2.0/TA 0.2/TA1.2/TA1.1
14
11
12
13
7
6
5
8
9
10
V
SS
/GND
P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3
P1.5/TA0.2/TA1.2/TA 0.1
P1.6/TA0.2/TA1.2/TA 1.1
V
CC
P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN
P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK
RST NMI SVMOUT/ /
TDO/P2.3/TA0.2/TA 1.2/CCI1.0
TDI/P2.2/TA0.2/TA1.2/CxOUT/CCI0.0
TMS/P2.1/TA 0.2/TA1.2/TA0.1
P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3
P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK
PW PACKAGE
(TOP VIEW)
Clock
System
2/(1)KB ROM 128B RAM
+96B CRAM
P2.0...P2.3GND/V
SS
MCLK
ACLK
SMCLK
I/O Port P2L
4 I/Os with
Interrupt
Capability
Watchdog
WDTA
32/16-Bit
Timer0_A3
3 CC
Registers
CPU &
Working
Registers
4W-JTAG
Analog-
Pool
Reset
Int-Logic
HF-OSC
Timer1_A3
3 CC
Register
V
CC
RST/NMI/SVMOUT
CLKIN
V
REF
TMS, TCK,
TDI, TDO
ULV-Ref.,
8-Bit ADC,
8-Bit DAC,
Comparator,
SVS
LF-OSC
ULV
Brownout
P1.0...P1.6
I/O Port P1L
7 I/Os with
Interrupt
Capability
Debug
support
CORE
MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010 www.ti.com
ORDERING INFORMATION
(1)
PACKAGED DEVICES
(2)
T
A
PLASTIC 14-PIN TSSOP (PW)
MSP430C091SPW
0ºC to 50ºC MSP430C092SPW
MSP430L092SPW
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/package.
Pin Designation, MSP430C091PW, MSP430C092PW
Functional Block Diagram, MSP430C092PW, MSP430C091PW
2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated