Datasheet

MSP430L092
MSP430C09x
SLAS673 –SEPTEMBER 2010 www.ti.com
Timer1_A3
Timer1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer1_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9. Timer1_A3 Signal Connections
INPUT PIN OUTPUT PIN
DEVICE INPUT MODULE INPUT MODULE DEVICE OUTPUT
NUMBER NUMBER
MODULE BLOCK
SIGNAL SIGNAL OUTPUT SIGNAL SIGNAL
PW PW
12 – P1.4 TA1CLK TACLK
ACLK ACLK
Timer NA NA
SMCLK SMCLK
12 – P1.4 TA1CLK TACLK
4 – P2.3 CCI1.0 CCI0A
9 – P1.3 CCI1.0 CCI0B TA1.0
CCR0 TA0
V
SS
GND
V
CC
V
CC
14 – P1.6 TA1.1 CCI1A 1 – P2.0
7 – P1.1 CCI1.1 CCI1B TA1.1 14 – P1.6
CCR1 TA1
V
SS
GND
V
CC
V
CC
1 – P2.0 TA1.2 CCI2A 1-4 – P2.0-P2.3
2 – P2.1 TA1.2 CCI2B 6-9 – P1.0-P1.3
CCR2 TA2 TA1.2
V
SS
GND 12-14 – P1.4-P1.6
V
CC
V
CC
16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated