Datasheet

MSP430L092
MSP430C09x
www.ti.com SLAS673 –SEPTEMBER 2010
Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 8. Timer0_A3 Signal Connections
INPUT PIN OUTPUT PIN
DEVICE INPUT MODULE INPUT MODULE DEVICE OUTPUT
NUMBER NUMBER
MODULE BLOCK
SIGNAL SIGNAL OUTPUT SIGNAL SIGNAL
PW PW
7 – P1.1 TA0CLK TACLK
ACLK ACLK
Timer NA NA
SMCLK SMCLK
7 – P1.1 TA0CLK TACLK
3 – P2.2 CCI0.0 CCI0A
8 – P1.2 CCI0.0 CCI0B
CCR0 TA0 TA0.0
V
SS
GND
V
CC
V
CC
13 – P1.5 TA0.1 CCI1A 2 – P2.1
6 – P1.0 CCI0.1 CCI1B 13 – P1.5
CCR1 TA1 TA0.1
V
SS
GND
V
CC
V
CC
1 – P2.0 TA0.2 CCI2A 1-4 – P2.0-P2.3
2 – P2.1 TA0.2 CCI2B 6-9 – P1.0-P1.3
CCR2 TA2 TA0.2
V
SS
GND 12-14 – P1.4-P1.6
V
CC
V
CC
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