MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 MIXED SIGNAL MICROCONTROLLER FEATURES 1 • • • • • • • • Ultra-Low Supply Voltage (ULV) Range – 0.9 V to 1.5 V (1 MHz) – 1.5 V to 1.65 V (4 MHz) Low Power Consumption – Active Mode (AM): 45 µA/MHz (1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com ORDERING INFORMATION (1) PACKAGED DEVICES (2) PLASTIC 14-PIN TSSOP (PW) TA MSP430C091SPW 0ºC to 50ºC MSP430C092SPW MSP430L092SPW (1) (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/package.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Pin Designation, MSP430L092PW PW PACKAGE (TOP VIEW) SPI_CS/TCK/P2.0/TA0.2/TA1.2/TA1.1 SPI_MOSI/TMS/P2.1/TA0.2/TA1.2/TA0.1 SPI_CLK/TDI/P2.2/TA0.2/TA1.2/CxOUT/CCI0.0 SPI_MISO/TDO/P2.3/TA0.2/TA1.2/CCI1.0 RST/NMI/SVMOUT P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK 14 13 12 11 10 9 8 1 2 3 4 5 6 7 P1.6/TA0.2/TA1.2/TA1.1 P1.5/TA0.2/TA1.2/TA0.1 P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK VCC VSS/GND P1.3/TA0.2/TA1.2/CxOUT/CCI1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 1. Terminal Functions TERMINAL NAME NO. I/O (1) DESCRIPTION JTAG test clock General-purpose digital I/O Timer0_A3 Out2 output TCK/P2.0/TA0.2/TA1.2/TA1.1 1 I/O Timer1_A3 Out2 output Timer1_A3 Out1 output Timer0_A3 CCR2 capture: CCI2A input, compare Timer1_A3 CCR2 capture: CCI2A input, compare JTAG test mode select General-purpose digital I/O Timer0_A3 Out2 output TMS/P2.1/TA0.2/TA1.2/TA0.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Table 1. Terminal Functions (continued) TERMINAL NAME NO. I/O (1) DESCRIPTION General-purpose digital I/O Timer0_A3 Out2 output Timer1_A3 Out2 output P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3 8 I/O ACLK output Timer0_A3 CCR0 capture: CCI0B input, compare Analog input A3 – A-Pool Analog output – A-Pool General-purpose digital I/O Timer0_A3 Out2 output Timer1_A3 Out2 output P1.3/TA0.2/TA1.2/CxOUT/CCI1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 4.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Special Function Registers (SFRs) The MSP430 SFRs are located in the lowest address space and can be accessed via word or byte formats. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR. SFR bit is not present in device.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Reset Pin Control Register 15 14 13 12 11 10 9 8 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 r0 SYSRSTRE SYSRSTUP SYSNMIES SYSNMI r0 r0 3 2 1 0 SYSRSTRE SYSRSTUP SYSNMIES SYSNMI r1 r1 r1 rw-0 r0 Indicates resistor present on RST pin Indicates pullup on RST pin Indicates NMI edge select NMI enable on RST/NMI pin Memory Organization Table 5.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 RAM Memory The RAM memory is split into three ranges for different purposes: application memory, lockable application memory, and calibration memory. Lockable application memory and calibration memory can be protected against accidental erasure by setting a dedicated lock bit in the special functions register (System Maintenance Register).
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com OSCOFF SELAx ACLK enable logic DIVAx 3 00 01 10 11 HF – OSC Divider /1/2/4/8/16/32 0 1 1 ACLK SCG0 SELMx CPUOFF MCLK enable logic LF-OSC DIVMx 3 00 01 10 11 0 CLKIN /2 Divider /1/2/4/8/16/32 0 1 1 SELSx 1 MCLK SCG1 SMCLK enable logic DIVSx DIVCLK 00 01 10 11 3 Divider /1/2/4/8/16/32 0 1 1 SMCLK VLOCLK Figure 1.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 RST/NMI/SVMOUT System The reset system of the MSP430x09x family features the functions reset input, reset output, NMI input, SVM output, and SVS input. ... Interrupt signals maskable/ unmaskable Interrupt Logic CPU irq nmi Resetsignals and violations PUC ... Reset Logic POR BOR SWBOR RST/NMI/ SVMOUT SWPOR RSTNMI Brownout Circuit & Delay clr from SVM logic SVMOE PortsOn SVSEN SVMPD set SVMPO Figure 2.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 7.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Timer0_A3 Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 8. Timer0_A3 Signal Connections INPUT PIN NUMBER PW 7 – P1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Timer1_A3 Timer1_A3 is a 16-bit timer/counter with three capture/compare registers. Timer1_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 9. Timer1_A3 Signal Connections INPUT PIN NUMBER PW 12 – P1.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 A-Pool The analog functions pool (A-Pool) provides a series of functions that can be configured to a digital-to-analog converter (DAC), multichannel analog-to-digital converter (ADC), supply voltage supervisor (SVS), and comparator. Input voltage dividers and an internal reference source allow a wide range of combined analog functions.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Versatile I/O Port P1, P2 The versatile I/O ports P1 and P2 feature device-dependent reset values. The reset values for the MSP430x09x devices are shown in Table 10. Table 10. Versatile Port Reset Values PORT NUMBER PxOUT PxDIR PxREN PxSEL0 PxSEL1 RESET PORTS ON COMMENT P1.0 0 0 0 0 0 PUC yes P1.0, input P1.1 0 0 0 0 0 PUC yes P1.1, input P1.2 0 0 0 0 0 PUC yes P1.2, input P1.3 0 0 0 0 0 PUC yes P1.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Table 11.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 11.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Absolute Maximum Ratings (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Voltage applied at VCC referenced to VSS (VAMR) –0.3 V to 1.90 V –0.3 V to VCC + 0.3 V Voltage applied to any pin (references to VSS) –0.3 V to 1.90 V Diode current at any device pin (2) ±2.5 mA Current derating factor when I/O ports are switched in parallel electrically and logically (3) 0.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Active Mode Supply Current (Into VCC) Excluding External Current (1) (2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz, Program executes in RAM, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 IAM,1MHz 1.3 V MAX 59 68 84 86 101 59 68 72 84 1.65 V 86 101 0.9 V 60 70 74 87 1.65 V 88 105 0.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Low-Power Mode Supply Current (Into VCC) Excluding External Current(1)(2) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA MIN 0.9 V 1.3 V ILPM2,1MHz fMCLK = fSMCLK = 1MHz, fACLK = 1MHz CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 fMCLK = fSMCLK = fACLK = 20 kHz CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 32 29 33 0.9 V 28 32 30 35 1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Ports P1 and P2, RST/NMI/SVMOUT over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC – 0.25 VCC = 1.65 V, IOH = –1 mA (1) for ports P1, P2 VCC – 0.15 VCC = 0.9 V, IOH = –300 µA (1) for ports P1, P2 VCC – 0.15 VIH VHYS Δt/Δv 0.2 (2) UNIT V 0.15 for ports P1, P2 V 0.07 VCC = 1.65 V 0.3 × VCC VCC = 0.9 V 0.25 × VCC VCC = 1.65 V 0.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Typical Characteristics – Outputs TYPICAL LOW-LEVEL OUTPUT VOLTAGE vs OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT VOLTAGE vs OUTPUT CURRENT 0 VCC = 0.9 V IOH – Typical High-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 3 0°C, 30°C, 50°C 2.5 2 1.5 1 0.5 0.05 VOL – Low-Level Output Voltage – V 0.1 -0.4 -0.6 -0.8 -1 0°C, 30°C, 50°C 0.85 0.875 VOH – High-Level Output Voltage – V Figure 4. Figure 5.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Typical Characteristics – Outputs (continued) TYPICAL LOW-LEVEL OUTPUT VOLTAGE vs LARGE SIGNAL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT VOLTAGE vs LARGE SIGNAL OUTPUT CURRENT 0 IOH – Typical High-Level Output Current – mA IOL – Typical Low-Level Output Current – mA 16 VCC = 1.65 V 14 12 10 30°C 8 6 4 2 0 VCC = 1.65 V -2 -4 -6 30°C -8 -10 -12 -14 -16 0 0.05 0.1 0.15 0.2 0.25 0.8 VOL – Low-Level Output Voltage – V Figure 8. Figure 9.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 High-Frequency Oscillator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN TYP MAX UNIT fHFOSC PARAMETER VCC = 0.9 V to 1.65 V (minimum trim range via register) 0.75 1 1.25 MHz fHFOSC VCC = 0.9 V to 1.65 V (trimmed at 30°C) 0.92 1 1.08 MHz Duty cycle VCC = 0.9 V to 1.65 V 45 50 55 % tSTART VCC = 0.9 V to 1.65 V 20 µs ΔfHFOSC/DT VCC = 0.9 V to 1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Low-Frequency Oscillator over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN TYP MAX fLFOSC PARAMETER VCC = 0.9 V to 1.65 V TEST CONDITIONS 6 20 45 Duty cycle VCC = 0.9 V to 1.65 V 45 50 tSTART VCC = 0.9 V to 1.65 V IOSC VCC = 0.9 V to 1.65 V, fLFOSC = 20 kHz UNIT kHz 55 % 500 µs 0.6 µA Typical Characteristics – Low-Frequency Oscillator FREQUENCY vs TEMPERATURE 40.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 A-POOL, External Reference Source over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VCC = 0.9 V to 1.65 V, ADC / DAC operational VREF VCC = 0.9 V to 1.65 V, ADC / DAC not operational IREF(Input) VCC = 0.9 V to 1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com A-POOL, Temperature Sensor over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP ISENSOR VCC = 0.9 V to 1.65 V TCSENSOR VCC = 0.9 V to 1.65 V, TA = 0°C to 50°C (ΔV/ΔT referenced to 30°C) 464 VOFFSET25 VCC = 0.9 V to 1.65 V at TA = 30°C 179 tSETTLE VCC = 0.9 V to 1.65 V (before start of conversion) VSENSOR (1) VCC = 0.9 V to 1.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 A-POOL, ADC-8 Counter over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fCNT VCC = 0.9 V to 1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com PORT SCHEMATICS Port P1, P1.0 Input/Output Pad Logic to Clock System to A-Pool PSELx=y # NSELx=y P1REN.x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT.x TA 0.2 TA 1.2 SMCLK 00 01 10 11 P1.0/TA0.2/TA1.2/ACLK/CCI0.1/A2/CLKIN P1SEL 0.x P1SEL 1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IFG.x P1IE.x P1IRQ.x Table 12. Port P1 (P1.0) Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1.0 (I/O) P1.0/TA0.2/TA1.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Port P1, P1.1 and P1.4 Input/Output Pad Logic to A-Pool PSELx=y # NSELx=y P1REN.x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT.x TA 0.2 TA 1.2 from Module 00 01 10 11 P1.1/TA0.2/TA1.2/SMCLK/CCI1.1/A1/TA0CLK P1.4/TA0.2/TA1.2/MCLK/A0/TA1CLK P1SEL 0.x P1SEL 1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IRQ.x Copyright © 2010, Texas Instruments Incorporated P1IFG.x P1IE.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 13. Port P1 (P1.1, P1.4) Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1.1 (I/O) P1.1/TA0.2/TA1.2/SMCLK/ CCI1.1/A1/TA0CLK 1 (1) 34 P1SEL0.x RSELx/ASE Lx I:0, O:1 0 0 0 1 0 1 0 Timer_A1.2 1 1 0 0 0 SMCLK 1 1 1 A1 X X X 1 TimerA0 CLK X ≠0 ≠0 X 0 ≠0 ≠0 X I:0, O:1 0 0 0 Timer_A0.2 1 0 1 0 Timer_A1.2 1 1 0 0 0 P1.4 (I/O) 4 P1SEL1.x Timer_A0.2 Timer A1, CCI1B P1.4/TA0.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Port P1, P1.2 and P1.3 Input/Output Pad Logic to A-Pool PSELx=y # NSELx=y from A -Pool from A -Pool P1REN .x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT .x TA 0.2 TA 1.2 from Module 00 01 10 11 P1.2/TA0.2/TA1.2/ACLK/CCI0.0/AOUT/A3 P1.3/TA0.2/TA1.2/CxOUT/CCI1.0/VREF/A3 P1SEL0.x P1SEL1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IRQ.x P1IFG .x P1IE.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Table 14. Port P1 (P1.2, P1.3) Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1.2 (I/O) P1.2/TA0.2/TA1.2/ACLK/ CCI0.0/AOUT/A3 2 36 RSELx/ASE Lx Analog Out 0 0 0 0 1 0 1 0 0 Timer_A1.2 1 1 0 0 0 ACLK 1 1 1 0 0 Timer A0, CCI0B 0 ≠0 ≠0 X X A3 X X X 3 X (2) X X X X 1 I:0, O:1 0 0 0 0 Timer_A0.2 1 0 1 0 0 Timer_A1.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Port P1, P1.5 and P1.6 Input/Output Pad Logic P1REN.x P1DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P1OUT.x TA 0.2 TA 1.2 Module X OUT 00 01 10 11 P1.5/TA 0.2/TA1.2/TA0.1 P1.6/TA 0.2/TA1.2/TA1.1 P1SEL0.x P1SEL1.x P1IN.x # EN1 EN2 Module X IN D P1IES.x Set Q P1IFG.x P1IE.x P1IRQ.x Table 15. Port P1 (P1.5, P1.6) Pin Functions PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL1.x P1SEL0.x I:0, O:1 0 0 Timer_A0.2 1 0 1 Timer_A1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Port P2, P2.0 to P2.2, Input/Output Pad Logic P2REN.x P2DIR.x Vss Vcc 00 01 10 11 0 1 PortsOn P2OUT.x TA 0.2 TA 1.2 Module X OUT 00 01 10 11 TCK/P2.0/TA0.2/TA1.2/TA 1.1 TMS/P2.1/TA0.2/TA 1.2/TA0.1 TDI/P2.2/TA0.2/TA 1.2/CxOUT/CCI0.0 P2SEL0.x P2SEL1.x P2IN.x to JTAG from JTAG # EN1 EN2 Module X IN D P2IES.x Set Q P2IRQ.x 38 Submit Documentation Feedback P2IFG.x P2IE.
MSP430L092 MSP430C09x www.ti.com SLAS673 – SEPTEMBER 2010 Table 16. Port P2 (P2.0 to P2.2) Pin Functions PIN NAME (P2.x) x FUNCTION P2.0 (I/O) TCK/P2.0/TA0.2/ TA1.2/TA1.1 0 1 2 P2SEL0.x JTAG Mode 0 0 0 1 0 1 0 Timer_A1.2 1 1 0 0 Timer_A1.1 1 1 1 0 Timer_A0.CCI2A and Timer_A1.CCI2A 0 ≠0 ≠0 0 JTAG-TCK (2) (3) (4) X X X 1 I:0, O:1 0 0 0 Timer_A0.2 1 0 1 0 Timer_A1.2 1 1 0 0 Timer_A0.1 1 1 1 0 Timer_A0.CCI2B and Timer_A1.
MSP430L092 MSP430C09x SLAS673 – SEPTEMBER 2010 www.ti.com Port P2, P2.3, Input/Output Pad Logic P2REN.x P2DIR.x Vss Vcc 00 01 10 11 from JTAG 0 1 PortsOn P2OUT.x TA 0.2 TA 1.2 TDO from JTAG 00 01 10 11 TDO/P2.3/TA0.2/TA 1.2/CCI1.0 P2SEL0.x P2SEL1.x P2IN.x to JTAG # EN1 EN2 Module X IN D P2IES.x Set Q P2IFG.x P2IE.x P2IRQ.x Table 17. Port P2 (P2.3) Pin Functions PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL1.x P2SEL0.x I:0, O:1 0 0 Timer_A0.2 1 0 1 Timer_A1.
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