Datasheet

PW28
(TOP VIEW)
1
DVCC
2
P1.0/TA0CLK/ACLK/A0
3
4
5
P1.3/ADC10CLK/VREF-/VEREF-/A3
6
7
8
P3.0/TA0.2
9
P3.1/TA1.0
10
P2.0/TA1.0
19
P3.5/TA0.1
20
P3.6/TA0.2
21
P3.7/TA1CLK
22
23
24
RST/NMI/SBWTDIO
25
TEST/SBWTCK
26
XOUT/P2.7
27
XIN/P2.6/TA0.1
28
DVSS
P1.6/TA0.1/ TDI/TCLKUCB0SOMI/UCB0SCL/A6/
P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA
P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI
P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO
P1.4/SMCLK/ TCK/VREF+/VEREF+/A4/UCB0STE/UCA0CLK
P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE
11
12
P2.2/TA1.1
13
P3.2/TA1.1
14
P3.3/TA1.2
15
P3.4/TA0.0
16
P2.3/TA1.0
17
P2.4/TA1.2
18
P2.5/TA1.2
P2.1/TA1.1
1
DVCC
2
P1.0/TA0CLK/ACLK/A0
3
4
5
P1.3/ADC10CLK/VREF-/VEREF-/A3
6
7
8
P2.0/TA1.0
9
P2.1/TA1.1
10
P2.2/TA1.1
11
P2.3/TA1.0
12
P2.4/TA1.2
13
P2.5/TA1.2
14
15
16
RST/NMI/SBWTDIO
17
TEST/SBWTCK
18
XOUT/P2.7
19
XIN/P2.6/TA0.1
20
DVSS
P1.6/TA0.1/ /TDI/TCLKUCB0SOMI/UCB0SCL/A6
P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA
P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI
P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO
P1.4/SMCLK/ /TCK/VREF+/VEREF+/A4UCB0STE/UCA0CLK
P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE
N20
PW20
(TOP VIEW)
MSP430G2x33
MSP430G2x03
www.ti.com SLAS734F –APRIL 2011–REVISED MAY 2013
Device Pinout, MSP430G2x03 and MSP430G2x33, 20-Pin Devices, TSSOP and PDIP
NOTE: ADC10 is available on MSP430G2x33 devices only.
NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.
Device Pinout, MSP430G2x03 and MSP430G2x33, 28-Pin Devices, TSSOP
NOTE: ADC10 is available on MSP430G2x33 devices only.
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