Datasheet

MSP430G2x52
MSP430G2x12
www.ti.com SLAS722G –DECEMBER 2010–REVISED MAY 2013
TERMINAL FUNCTIONS
Table 2. Terminal Functions
TERMINAL
NO.
I/O DESCRIPTION
NAME
14 16 20
PW RSA N, PW
P1.0/ General-purpose digital I/O pin
TA0CLK/ Timer0_A, clock signal TACLK input
ACLK/ 2 1 2 I/O ACLK signal output
A0/ ADC10 analog input A0
(1)
CA0 Comparator_A+, CA0 input
P1.1/ General-purpose digital I/O pin
TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output
3 2 3 I/O
A1/ ADC10 analog input A1
(1)
CA1 Comparator_A+, CA1 input
P1.2/ General-purpose digital I/O pin
TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output
4 3 4 I/O
A2/ ADC10 analog input A2
(1)
CA2 Comparator_A+, CA2 input
P1.3/ General-purpose digital I/O pin
ADC10CLK/ ADC10, conversion clock output
(1)
CAOUT/ Comparator_A+, output
5 4 5 I/O
A3/ ADC10 analog input A3
(1)
VREF-/VEREF-/ ADC10 negative reference voltage
(1)
CA3 Comparator_A+, CA3 input
P1.4/ General-purpose digital I/O pin
SMCLK/ SMCLK signal output
TA0.2/ Timer0_A, capture: CCI2A input, compare: Out2 output
A4/ 6 5 6 I/O ADC10 analog input A4
(1)
VREF+/VEREF+/ ADC10 positive reference voltage
(1)
CA4/ Comparator_A+, CA4 input
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ Timer0_A, compare: Out0 output
SCLK/ USI: clk input in I2C mode; clk in/output in SPI mode
7 6 7 I/O
A5/ ADC10 analog input A5
(1)
CA5/ Comparator_A+, CA5 input
TMS JTAG test mode select, input terminal for device programming and test
P1.6/ General-purpose digital I/O pin
TA0.1/ Timer0_A, compare: Out1 output
SDO/ USI: Data output in SPI mode
SCL/ 8 7 14 I/O USI: I2C clock in I2C mode
A6/ ADC10 analog input A6
(1)
CA6/ Comparator_A+, CA6 input
TDI/TCLK JTAG test data input or test clock input during programming and test
(1) Available only on MSP430G2x52 devices.
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